Trench-gate semiconductor device and method of manufacturing

• US 7,232,726 B2
• Filed: 05/21/2003
• Issued: 06/19/2007
• Est. Priority Date: 05/31/2002
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Peake, Steven T., Rutter, Philip
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US10/515,749
• Publication Number:
  US 20050208722A1
• Time in Patent Office: 1,490 Days
• Field of Search: 438/137, 438/138, 438/270, 438/271, 438/273, 438/589, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove into the semiconductor body for receiving the gate, and etching a second groove into the top major surface of the semiconductor body, the second groove extending from the first groove and being narrower than the first groove. The invention enables better control of the vertical extent of the gate below the top major surface of the semiconductor body.

Claims

1. A method of manufacturing a trench-gate semiconductor device, the device having a semiconductor body defining a first portion of a trench having an insulated gate therein, a second portion of the trench extending from the bottom of the first trench portion, the semiconductor:

body comprising a source region and a drain region of a first conductivity type which are separated by a channel-accommodating region adjacent to the first trench portion, the drain region comprising a drain drift region and a drain contact region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region doped to a lesser extent than the drain contact region, and a field plate in the second portion of the trench between the gate and the drain contact region, the method comprisinging the steps of;

(a) etching a first groove into the semiconductor body;

(b) forming spacers adjacent the sidewalls of the first groove which define a window therebetween;

(c) etching a second groove into the semiconductor body through the window between the spacers, the second groove extending from the bottom of the first groove towards the drain contact region and being narrower than the first groove; and

(d) forming a field plate insulating layer by oxidising the bottom and sidewalls of the second groove;

(e) providing the field plate over the field plate insulating layer in the second groove by filling the first and second grooves with electrode material, and etching it back until the field plate insulating layer is exposed;

(f) removing the spacers;

(g) forming a gate insulating layer over the field plate and at the bottom and sidewalls of the first groove; and

(h) providing the gate over the gate insulating layer.

2. The method as recited in claim 1, further comprising the steps of:

(i) removing the spacers;

(j) forming a gate insulating layer over the bottom and sidewalls of the first groove and then

(k) filling the first and second grooves with electrode material to form the gate and field plate.

3. A trench-gate semiconductor device manufactured according to the method of claim 1, wherein the width of the first trench portion is greater than the width of the second trench portion.

4. A trench-gate semiconductor device manufactured according to the method of claim 1 wherein the field plate is connected to the source region.

5. A trench-gate semiconductor device manufactured according to the method of claim 1 wherein the field plate is connected to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region.

6. A module comprising a trench-gate semiconductor device as-recited in claim 5 wherein the field plate is connected to an internal voltage line of the module.

7. The trench-gate semiconductor device as recited in claim 5, wherein an additional external terminal is provided which is electrically connected to the field plate.

8. The trench-gate semiconductor device as recited in claim 5, wherein the bias potential is around 60 to 100% of the bulk breakdown voltage of the drain drift region.

9. The trench gate semiconductor device as recited in claim 8, wherein the bias potential is around 80% of the bulk breakdown voltage of the drain drift region.

10. The module as recited in claim 6, wherein an additional external terminal is provided which is electrically connected to the field plate.

11. The module as recited in claim 6, wherein the bias potential is around 60 to 100% of the bulk breakdown voltage of the drain drift region.

12. The trench-gate semiconductor device as recited in claim 7, wherein, the bias potential is around 60 to 100% of the bulk breakdown voltage of the drain drift region.