Method for manufacturing a double bitline implant

• US 7,232,729 B1
• Filed: 05/06/2003
• Issued: 06/19/2007
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Wong, Nga-Ching
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US10/431,321
• Time in Patent Office: 1,505 Days
• Field of Search: 257335-343, 257/E21.135, 438/45, 438/163, 438/194, 438/217, 438229-232, 438/289, 438301-303, 438/306, 438/510, 438/514, 438/517, 438/542, 438546-548, 438/305
• US Class Current: 438/301
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep more heavily doped region, disposed laterally within the shallow heavily doped region and vertically within and below the shallow heavily doped region. In an optional feature of the present invention, the method further comprises selectively implanting a second impurity, wherein the doping profile of the deep more heavily doped region is graded.

Claims

1. A method of fabricating a doped semiconductor region comprising:

selectively implanting a first impurity of a first conductivity type to form a first heavily doped region;

selectively implanting said first impurity to form a second heavily doped region, wherein said second region is disposed laterally within said first region and vertically within and below said first region, and wherein said second region is more heavily doped than said first region;

selectively implanting a second impurity of a second conductivity type to form a third doped region, wherein said second impurity has a higher diffusivity than said first impurity, and wherein said second conductivity type is not the same as said first conductivity type, wherein said third region is disposed within said second heavily doped region and within and vertically below said first region, wherein said first, second and third doped regions form a compound doped region; and

annealing, wherein a doping profile of said second heavily doped region is graded along a junction region, wherein said graded doping profile results in decreased junction capacitance.

2. The method according to claim 1, wherein said selectively implanting said first impurity to form said first heavily doped region comprises:

forming a first implant barrier having a first opening; and

forming a first doped region in a first portion of a substrate exposed by said first opening.

3. The method according to claim 2, wherein said selectively implanting said first impurity to form said second heavily doped region comprises:

forming a second implant barrier, having a second opening disposed within said first opening; and

forming a second doped region in a second portion of said substrate exposed by said second opening.

4. The method according to claim 1 wherein said first impurity of said first conductivity type is a donor impurity, and wherein said second impurity of said second conductivity type is an acceptor impurity.

5. The method according to claim 1 wherein said first impurity of said first conductivity type is an acceptor impurity, and wherein said second impurity of said second conductivity type is a donor impurity.

6. A method of forming a compound doped structure comprising:

forming a first implant barrier on a substrate, having a first opening;

implanting said substrate exposed by said first opening with a first conductivity type of impurity to form a first doped region;

forming a second implant barrier, having a second opening disposed within said first opening;

implanting said substrate exposed by said second opening with said first conductivity type of impurity to form a second doped region, wherein said first conductivity type of impurity has a first diffusivity, and wherein said second doped region is disposed laterally within said first region and vertically within and below said first region, and wherein said second region is more heavily doped than said first region;

implanting said substrate exposed by said second opening with a second type conductivity of impurity to form a third doped region, wherein said second type of impurity has a second diffusivity, wherein said second type of impurity is not the same as said first type of impurity, wherein said third doped region is disposed within said second heavily doped region and within and vertically below said first region, and wherein said first, second and third doped regions form a compound doped region;

annealing said substrate, wherein a first doped region disposed at a first depth and aligned with said first opening is formed, and wherein said second doped region comprises a graded doping profile as a function of said first diffusivity and said second diffusivity, wherein said graded doping profile results in decreased function capacitance.

7. The method recited in claim 6, wherein forming said first implant barrier comprises forming one or more structures consisting of a gate, a control gate, a floating gate, a bitline, and a wordline.

8. The method recited in claim 7, wherein forming said gate comprises:

depositing a polysilicon layer;

depositing a resist layer;

patterning said resist layer;

selectively etching said polysilicon layer.

9. The method recited in claim 7, wherein forming said second implant barrier comprises forming a spacer.

10. The method recited in claim 9, wherein forming said spacer comprises:

depositing a nitride layer;

depositing a resist layer;

patterning said resist layer;

selectively etching said nitride layer.

11. The method recited in claim 6, wherein said first conductivity type of impurity is a donor impurity, and wherein said second type conductivity of impurity is an acceptor impurity.

12. The method recited in claim 6, wherein said first conductivity type of impurity is an acceptor impurity, and wherein said second type conductivity of impurity is a donor impurity.