Three-dimensional memory device incorporating segmented bit line memory array

• US 7,233,024 B2
• Filed: 03/31/2003
• Issued: 06/19/2007
• Est. Priority Date: 03/31/2003
• Status: Expired due to Term

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca, Ilkbahar, Alper
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US10/403,752
• Publication Number:
  US 20040188714A1
• Time in Patent Office: 1,541 Days
• Field of Search: 365/51, 365/63, 36518505-18517, 365/230.03, 365/230.04, 257/390, 257/499, 257/910, 257/74
• US Class Current: 257/74
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

Claims

1. An integrated circuit comprising:

a three-dimensional memory array having a respective plurality of word lines on each of at least one layer of the memory array, having a respective plurality of bit line segments on each of at least two layers of the memory array, defining a memory layer for each vertically adjacent word line layer and segmented bit line layer; and

a respective plurality of global bit lines on each of at least a first global bit line layer;

a respective plurality of memory segments on each of said memory layers, each memory segment comprising

a respective plurality of memory cells coupled to a respective bit line segment; and

a respective segment switch device for coupling the respective bit line segment to an associated global bit line by way of a vertical connection which is shared by at least one memory segment on each of at least two memory layers.

2. The integrated circuit of claim 1 comprising a single global bit line layer disposed below the memory layers.

3. The integrated circuit of claim 1 wherein at least one word line or bit line layer is shared by two vertically adjacent memory layers.

4. The integrated circuit of claim 3 wherein at least one word line layer is shared by two bit line layers, both such bit line layers associated with a single global bit line layer.

5. The integrated circuit of claim 1 comprising memory segments including a respective bias line segment coupled to an associated global bias line.

6. The integrated circuit of claim 5 comprising memory cells including a capacitor for storing memory state.

7. The integrated circuit of claim 1 wherein at least two bit line segments on a given layer that do not have word lines in common, each share a vertical connection to an associated global bit line.

8. The integrated circuit of claim 7 comprising passive element memory cells.

9. The integrated circuit of claim 7 comprising memory cells including a switch device.

10. The integrated circuit of claim 7 wherein at least two bit line segments on a given layer having a first plurality of word lines in common share a vertical connection to an associated global bit line with at least two other bit line segments on the given layer having a second plurality of word lines in common.

11. The integrated circuit of claim 1 further comprising a second global bit line layer.

12. The integrated circuit of claim 11 wherein half of the bit line segments on a given layer are associated with the first global bit line layer, and the other half associated with the second global bit line layer.

13. The integrated circuit of claim 11 wherein:

bit line segments on a given layer are associated with either the first global bit line layer or the second global bit line layer; and

bit line segments on each of a first set of memory layers are associated with the first global bit line layer, and bit line segments on each of a second set of memory layers are associated with the second global bit line layer.

14. The integrated circuit of claim 11 wherein at least one word line layer is shared by two bit line layers, one such bit line layer associated with the first global bit line layer, and the other such bit line layer associated with the second global bit line layer.

15. The integrated circuit of claim 1 wherein the bit line segments on a given layer are interleaved such that at least two bit line segments sharing word lines in common are coupled at opposite ends thereof to an associated global bit line.

16. The integrated circuit of claim 15 wherein a pair of interleaved bit line segments on the given layer are coupled at opposite ends thereof to a single global bit line.

17. The integrated circuit of claim 16 comprising passive element memory cells.

18. The integrated circuit of claim 1 wherein at least two bit line segments on a given layer having word lines in common share a vertical connection to an associated global bit line.

19. The integrated circuit of claim 18 wherein each of the at least two bit line segments on a given layer having word lines in common that share a vertical connection to an associated global bit line, have a different segment control signal for its respective segment switch device.

20. The integrated circuit of claim 19 comprising memory cells including a charge storage dielectric.

21. The integrated circuit of claim 19 comprising memory cells including a capacitor for storing memory state.

22. The integrated circuit of claim 19 comprising memory cells including a ferro-electric material.

23. The integrated circuit of claim 1 further comprising:

a respective plurality of global bias lines on at least a first global bias line layer;

wherein each memory segment further comprises a respective bias line segment and a respective bias switch device for coupling the respective bias line segment to an associated global bias line.

24. The integrated circuit of claim 23 comprising memory cells including a ferro-electric material.

25. The integrated circuit of claim 23 wherein the global bias lines run parallel to the word lines.

26. The integrated circuit of claim 23 wherein the bit line segments on a given layer are interleaved such that at least two bit line segments sharing word lines in common are coupled at opposite ends thereof to an associated global bit line.

27. The integrated circuit of claim 23 wherein at least two memory segments on a given layer that do not have word lines in common, each share a vertical connection to an associated global bias line.

28. The integrated circuit of claim 27 wherein at least two memory segments on a given layer having a first plurality of word lines in common share a vertical connection to an associated global bias line with at least two other memory segments on the given layer having a second plurality of word lines in common.

29. The integrated circuit of claim 23 wherein:

the bias line segments on a given layer are associated with either a first global bias line layer or a second global bias line layer; and

the bias line segments on each of a first set of memory layers are associated with the first global bias line layer, and the bias line segments on each of a second set of memory layers are associated with the second global bias line layer.

30. The integrated circuit of claim 29 wherein:

at least one word line layer is shared by two bit line layers; and

the bias line segments on half of the memory layers are associated with the first global bias line layer, and the bias line segments on the other half are associated with the second global bias line layer.

31. The integrated circuit of claim 23 wherein at least two memory segments on a given layer having word lines in common share a vertical connection to an associated global bias line.

32. The integrated circuit of claim 31 wherein each of the at least two memory segments on a given layer having word lines in common that share a vertical connection to an associated global bias line, have a respective bias switch device controlled by the same bias segment control signal.

33. The integrated circuit of claim 31 wherein each of the at least two memory segments on a given layer having word lines in common that share a vertical connection to an associated global bias line, have a different bias segment control signal for its respective bias switch device.

34. The integrated circuit of claim 33 comprising SONOS memory cells.

35. The integrated circuit of claim 33 comprising memory cells having a ferro-electric material.

36. The integrated circuit of claim 33 comprising memory cells having a switch device with a permanently modifiable threshold voltage.

37. An integrated circuit comprising:

a three-dimensional memory array having a respective plurality of word lines on each of at least one layer of the memory array, having a respective plurality of bit line segments on each of at least two layers of the memory array, defining a memory layer for each vertically adjacent word line layer and segmented bit line layer; and

a respective plurality of global bit lines on a first global bit line layer disposed below the memory layers;

a respective plurality of global bit lines on a second global bit line layer disposed above the memory layers; and

a respective plurality of memory segments on each of said memory layers, each memory segment comprising

a respective plurality of memory cells coupled to a respective bit line segment; and

a respective segment switch device for coupling the respective bit line segment to an associated global bit line by way of a vertical connection which is shared by at least one memory segment on each of at least two memory layers.