Integrated circuit and associated packaged integrated circuit having an integrated marking apparatus

• US 7,233,161 B2
• Filed: 06/10/2005
• Issued: 06/19/2007
• Est. Priority Date: 12/14/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zettler, Thomas
• Primary Examiner(s): Nguyen; Vinh P.
• Application Number:
  US11/150,625
• Publication Number:
  US 20050225348A1
• Time in Patent Office: 739 Days
• Field of Search: 324760-766, 324/158.1, 714731-733, 714/42, 365200-201
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit and an associated packaged integrated circuit are provided which improve testability and reduce the test costs. The integrated circuit contains an integrated functional circuit to be tested, a test interface that connects the functional circuit to a test apparatus which performs a function test on the functional circuit to ascertain a test result, and an integrated self-marking apparatus that produces a marking on the basis of the test result. The marking can be magnetic or optical or electrical, volatile or nonvolatile, and thermally or electrically activated. The test apparatus includes an external test unit or an integrated self-test unit. Nonvolatile memory elements store the test results in a buffer.

Claims

1. An integrated circuit comprising

an integrated functional circuit to be tested;

a test interface that connects the functional circuit to a test apparatus which performs a function test on the functional circuit to ascertain a test result; and

an integrated self-marking apparatus that produces a magnetically readable marking on the basis of the test result.

2. The integrated circuit as claimed in claim 1, wherein the integrated self-marking apparatus comprises a magnetic marking element that produces the magnetically readable marking and a marking element activation unit that activates the marking element.

3. The integrated circuit as claimed in claim 2, wherein the magnetic marking element comprises a thermosensitive marking element, and the marking element activation unit brings about a change in temperature.

4. The integrated circuit as claimed in claim 2, wherein the magnetic marking element comprises a field sensitive marking element, and the marking element activation unit brings about a change in an electrical field.

5. The integrated circuit as claimed in claim 2, wherein the marking element comprises at least one of an electrical marking element that produces an electrically readable marking or an optical marking element that produces an optically readable marking.

6. The integrated circuit as claimed in claim 1, wherein the magnetically readable marking comprises a nonvolatile marking.

7. The integrated circuit as claimed in claim 1, wherein the test apparatus comprises at least one of an external test unit or an integrated self-test unit.

8. The integrated circuit as claimed in claim 1, wherein the integrated self-marking apparatus has a multiplicity of self-marking apparatus components that produce marking components on the basis of test result components from the integrated functional circuit.

9. A packaged integrated circuit comprising an integrated circuit as claimed in claim 1 which is packaged in a package, wherein the package comprises, in a region of the self-marking apparatus, a material which permits the marking on the integrated circuit to be read.

10. The packaged integrated circuit as claimed in claim 9, wherein the package is permeable to magnetic fields in the region of the self-marking apparatus.

11. The packaged integrated circuit as claimed in claim 9, wherein the test interface in the integrated circuit can be actuated by means of connection pins on the package.

12. A packaged integrated circuit comprising:

an integrated circuit to be tested;

a test interface that connects the integrated circuit to a test apparatus which performs a function test for the integrated circuit to ascertain a test result; and

a package self-marking apparatus, formed in a package, that produces a magnetically readable package marking on the basis of the test result.

13. The packaged integrated circuit as claimed in claim 12, wherein the package self-marking apparatus comprises a magnetic marking element that produces the magnetically readable marking and a marking element activation unit that activates the marking element.

14. An integrated circuit comprising

an integrated functional circuit to be tested:

a test interface that connects the functional circuit to a test apparatus which performs a function test on the functional circuit to ascertain a test result

an integrated self-marking apparatus that contains a multiplicity of self-marking apparatus components that produce marking components of different types on the basis of test result components from the integrated functional circuit wherein the self-marking apparatus comprises marking elements that produce the marking components and at least one marking element activation unit that activates the marking components; and

wherein at least one of the marking elements comprises a magnetic marking element that produces a magnetically readable marking component and a marking element activation unit that activates the marking component.

15. The integrated circuit as claimed in claim 14, wherein at least one of the marking elements comprises a thermosensitive marking element, and the at least one marking element activation unit comprises a thermosensitive marking element activation unit that brings about a change in temperature.

16. The integrated circuit as claimed in claim 14, wherein the marking components comprise a nonvolatile marking component.

17. The integrated circuit as claimed in claim 14, wherein the test apparatus comprises at least one of an external test unit or an integrated self-test unit.

18. The integrated circuit as claimed in 14, wherein at one of the marking components can be detected contactlessly.

19. An integrated circuit comprising

an integrated functional circuit to be tested:

a test interface that connects the functional circuit to a test apparatus which performs a function test on the functional circuit to ascertain a test result

an integrated self-marking apparatus that contains a multiplicity of self-marking apparatus components that produce marking components of different types on the basis of test result components from the integrated functional circuit;

wherein the self-marking apparatus comprises marking elements that produce the marking components and at least one marking element activation unit that activates the marking components; and

wherein at least one of the marking elements comprises a field sensitive marking element, and the at least one marking element activation unit comprises a field sensitive marking element activation unit that brings about a change in an electrical field.