NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

• US 7,233,522 B2
• Filed: 12/05/2003
• Issued: 06/19/2007
• Est. Priority Date: 12/31/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G., Nallamothu, Sucheta, Walker, Andrew J., Chen, En-Hsing, Ilkbahar, Alper
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/729,831
• Publication Number:
  US 20040145024A1
• Time in Patent Office: 1,292 Days
• Field of Search: 365/185.02, 365/185.17, 365/185.18, 365/185.23, 365/185.28, 365/185.29
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Claims

1. A method of operating an integrated circuit having a memory array including at least one plane of memory cells, said memory cells comprising switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

then

capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;

wherein the biasing step comprises;

(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and

then

(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;

wherein the method further comprises;

(e) coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;

(f) coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;

(g) turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string; and

(h) turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

2. The method of claim 1 wherein:

the respective second group of at least one series selection device at the second end of the selected and unselected NAND strings each includes at least two such selection devices, each device driven by one of a second group of select signals; and

the method further comprises driving at least two of the second group of select signals to different voltages chosen to reduce leakage current from the unselected NAND string to the respective second array line associated therewith, and to reduce leakage current from the selected NAND string to the respective second array line associated therewith, when the selected word line is driven to the word line programming voltage.

3. The method of claim 2 wherein:

the respective first array line for each NAND string comprises a respective global bit line associated therewith; and

the respective second array line for each NAND string comprises a shared bias node.

4. The method of claim 3 wherein:

the respective first group of at least one series selection device of each NAND string within the selected block numbers one such selection device; and

the respective second group of at least one series selection device of each NAND string within the selected block includes at least a first and second such selection devices.

5. The method of claim 4 wherein:

for the second group of at least one series selection device of each NAND string within the selected block, the select signal applied to the first selection device conveys a voltage that is less than the threshold voltage of the first selection device, relative to a voltage on the shared bias node, and the select signal applied to the second selection device conveys a voltage that is greater than the threshold voltage of the second selection device, relative to the shared bias node voltage.

6. The method of claim 3 further comprising:

during at least a programming pulse on the selected word line, biasing the shared bias node to a voltage between the bit line inhibit voltage and the bit line programming voltage.

7. The method of claim 2 wherein:

for the selected NAND string, the respective first array line comprises a respective global bit line associated therewith, and the respective second array line comprises a shared bias node; and

for the unselected NAND string, the respective first array line comprises a shared bias node associated therewith, and the respective second array line comprises a respective global bit line.

8. The method of claim 7 wherein:

the respective first group of at least one series selection device of each NAND string numbers at least two such selection devices; and

the respective second group of at least one series selection device of each NAND string numbers at least two such selection devices.

9. The method of claim 2 further comprising:

driving unselected word lines associated with memory cells between the selected memory cell and the second end of the selected NAND string to a third passing voltage closer to the programming voltage than is the second passing voltage at least during any selected word line programming pulse, to thereby reduce programming stress across such unselected memory cells.

10. The method of claim 9 further comprising:

applying multiple selected word line programming pulses, and re-establishing the voltage bias of the half-selected memory cell channel region before each such programming pulse.

11. The method of claim 10 wherein at least one of the multiple selected word line programming pulses is less than 20 microseconds in duration.

12. A method of operating an integrated circuit having a memory array including at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

then

capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;

wherein the biasing step comprises;

(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and

then

(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;

wherein the method further comprises;

(e) coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;

(f) coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;

(g) turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string; and

(h) turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

13. The method of claim 12 wherein:

the respective second group of at least one series selection device at the second end of the selected and unselected NAND strings each includes at least two such selection devices, each device driven by one of a second group of select signals; and

the method further comprises driving at least two of the second group of select signals to different voltages chosen to reduce leakage current from the unselected NAND string to the respective second array line associated therewith, and to reduce leakage current from the selected NAND string to the respective second array line associated therewith, when the selected word line is driven to the word line programming voltage.

14. The method of claim 13 wherein:

the respective first array line for each NAND string comprises a respective global bit line associated therewith; and

the respective second array line for each NAND string comprises a shared bias node.

15. The method of claim 14 wherein:

the respective first group of at least one series selection device of each NAND string within the selected block numbers one such selection device; and

the respective second group of at least one series selection device of each NAND string within the selected block includes at least a first and second such selection devices.

16. The method of claim 15 wherein:

for the second group of at least one series selection device of each NAND string within the selected block, the select signal applied to the first selection device conveys a voltage that is less than the threshold voltage of the first selection device, relative to a voltage on the shared bias node, and the select signal applied to the second selection device conveys a voltage that is greater than the threshold voltage of the second selection device, relative to the shared bias node voltage.

17. The method of claim 14 further comprising:

during at least a programming pulse on the selected word line, biasing the shared bias node to a voltage between the bit line inhibit voltage and the bit line programming voltage.

18. The method of claim 13 wherein:

for the selected NAND string, the respective first array line comprises a respective global bit line associated therewith, and the respective second array line comprises a shared bias node; and

for the unselected NAND string, the respective first array line comprises a shared bias node associated therewith, and the respective second array line comprises a respective global bit line.

19. The method of claim 18 wherein:

the respective first group of at least one series selection device of each NAND string numbers at least two such selection devices; and

the respective second group of at least one series selection device of each NAND string numbers at least two such selection devices.

20. The method of claim 13 further comprising:

driving unselected word lines associated with memory cells between the selected memory cell and the second end of the selected NAND string to a third passing voltage closer to the programming voltage than is the second passing voltage at least during any selected word line programming pulse, to thereby reduce programming stress across such unselected memory cells.

21. The method of claim 20 further comprising:

applying multiple selected word line programming pulses, and re-establishing the voltage bias of the half-selected memory cell channel region before each such programming pulse.

22. The method of claim 21 wherein at least one of the multiple selected word line programming pulses is less than 20 microseconds in duration.

23. An integrated circuit comprising:

a memory array having at least one plane of memory cells, said memory cells comprising switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings; and

means for biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

means for capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;

wherein the means for biasing comprises;

means for conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

means for coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

means for turning on the half-selected memory cell and any intevening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and

means for decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;

said integrated circuit further comprising;

means for coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;

means for coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;

means for turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string; and

means for turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

24. The integrated circuit of claim 23 wherein:

the respective second group of at least one series selection device at the second end of the selected and unselected NAND strings each includes at least two such selection devices, each device driven by one of a second group of select signals; and

at least two of the second group of select signals are driven to different voltages chosen to reduce leakage current from the unselected NAND string to the respective second array line associated therewith, and to reduce leakage current from the selected NAND string to the respective second array line associated therewith, when the selected word line is driven to the word line programming voltage.

25. The integrated circuit of claim 24 wherein:

the respective first array line for each NAND string comprises a respective global bit line associated therewith; and

the respective second array line for each NAND string comprises a shared bias node.

26. The integrated circuit of claim 25 wherein:

the respective first group of at least one series selection device of each NAND string within the selected block numbers one such selection device; and

the respective second group of at least one series selection device of each NAND string within the selected block includes at least a first and second such selection devices.

27. The integrated circuit of claim 26 wherein:

for the second group of at least one series selection device of each NAND string within the selected block, the select signal applied to the first selection device conveys a voltage that is less than the threshold voltage of the first selection device, relative to a voltage on the shared bias node, and the select signal applied to the second selection device conveys a voltage that is greater than the threshold voltage of the second selection device, relative to the shared bias node voltage.

28. The integrated circuit of claim 25 wherein:

during at least a programming pulse on the selected word line, the shared bias node is driven to a voltage between the bit line inhibit voltage and the bit line programming voltage.

29. The integrated circuit of claim 24 wherein:

for the selected NAND string, the respective first array line comprises a respective global bit line associated therewith, and the respective second array line comprises a shared bias node; and

for the unselected NAND string, the respective first array line comprises a shared bias node associated therewith, and the respective second array line comprises a respective global bit line.

30. The integrated circuit of claim 29 wherein:

the respective first group of at least one series selection device of each NAND string numbers at least two such selection devices; and

the respective second group of at least one series selection device of each NAND string numbers at least two such selection devices.

31. The integrated circuit of claim 24 wherein:

unselected word lines associated with memory cells between the selected memory cell and the second end of the selected NAND string are driven to a third passing voltage closer to the programming voltage than is the second passing voltage at least during any selected word line programming pulse, to thereby reduce programming stress across such unselected memory cells.

32. The integrated circuit of claim 31 configured to apply multiple selected word line programming pulses, and to re-establish the voltage bias of the half-selected memory cell channel region before each such programming pulse.

33. The integrated circuit of claim 32 wherein at least one of the multiple selected word line programming pulses is less than 20 microseconds in duration.

34. An integrated circuit comprising:

a memory array having at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings; and

means for biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

means for capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;

wherein the means for biasing comprises;

means for conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

means for coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

means for turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and

means for decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage;

said integrated circuit further comprising;

means for coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;

means for coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line;

means for turning off at least one device of a second group of at least one series selection device at a second end of the unselected NAND string opposite the first end, said second group of at least one series selection device for coupling said unselected NAND string to a respective second array line associated with the unselected NAND string; and

means for turning off at least one device of a second group of at least one series selection device at a second end of the selected NAND string opposite the first end, said second group of at least one series selection device for coupling said selected NAND string to a respective second array line associated with the selected NAND string.

35. The integrated circuit of claim 34 wherein:

the respective second group of at least one series selection device at the second end of the selected and unselected NAND strings each includes at least two such selection devices, each device driven by one of a second group of select signals; and

at least two of the second group of select signals are driven to different voltages chosen to reduce leakage current from the unselected NAND string to the respective second array line associated therewith, and to reduce leakage current from the selected NAND string to the respective second array line associated therewith, when the selected word line is driven to the word line programming voltage.

36. The integrated circuit of claim 35 wherein:

the respective first array line for each NAND string comprises a respective global bit line associated therewith; and

the respective second array line for each NAND string comprises a shared bias node.

37. The integrated circuit of claim 36 wherein:

the respective first group of at least one series selection device of each NAND string within the selected block numbers one such selection device; and

the respective second group of at least one series selection device of each NAND string within the selected block includes at least a first and second such selection devices.

38. The integrated circuit of claim 37 wherein:

for the second group of at least one series selection device of each NAND string within the selected block, the select signal applied to the first selection device conveys a voltage that is less than the threshold voltage of the first selection device, relative to a voltage on the shared bias node, and the select signal applied to the second selection device conveys a voltage that is greater than the threshold voltage of the second selection device, relative to the shared bias node voltage.

39. The integrated circuit of claim 36 wherein:

during at least a programming pulse on the selected word line, the shared bias node is biased to a voltage between the bit line inhibit voltage and the bit line programming voltage.

40. The integrated circuit of claim 35 wherein:

for the selected NAND string, the respective first array line comprises a respective global bit line associated therewith, and the respective second array line comprises a shared bias node; and

for the unselected NAND string, the respective first array line comprises a shared bias node associated therewith, and the respective second array line comprises a respective global bit line.

41. The integrated circuit of claim 40 wherein:

the respective first group of at least one series selection device of each NAND string numbers at least two such selection devices; and

the respective second group of at least one series selection device of each NAND string numbers at least two such selection devices.

42. The integrated circuit of claim 35 wherein:

unselected word lines associated with memory cells between the selected memory cell and the second end of the selected NAND string are driven to a third passing voltage closer to the programming voltage than is the second passing voltage at least during any selected word line programming pulse, to thereby reduce programming stress across such unselected memory cells.

43. The integrated circuit of claim 42 configured to:

apply multiple selected word line programming pulses, and re-establish the voltage bias of the half-selected memory cell channel region before each such programming pulse.

44. The integrated circuit of claim 43 wherein at least one of the multiple selected word line programming pulses is less than 20 microseconds in duration.