System for erasing nonvolatile memory

• US 7,233,529 B2
• Filed: 07/09/2004
• Issued: 06/19/2007
• Est. Priority Date: 08/27/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Matsubara, Ken, Takase, Yoshinori, Fujisawa, Tomoyuki
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): WEINBERG, MICHAEL J
• Application Number:
  US10/887,077
• Publication Number:
  US 20050047215A1
• Time in Patent Office: 1,075 Days
• Field of Search: 365/185.24, 365/185.29, 365/185.28, 365/185.3
• US Class Current: 365/185.3
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

Claims

1. A semiconductor integrated circuit comprising:

nonvolatile memory cells each having a threshold voltage which can be changed reversibly by electrical erasing and writing; and

a control circuit for controlling the changing of the threshold voltage of each said nonvolatile memory cell,

wherein said control circuit controls an erase process of performing simultaneous erasing to a plurality of the nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to a specified one of the nonvolatile memory cells assigned to said one unit when a limit of a threshold voltage distribution in an erase direction is determined to exceed a first level before an over-erase limit in the erase direction, and a second write process of performing writing to a specified one of the nonvolatile memory cells assigned to said one unit when the limit of said threshold voltage distribution in the erase direction is determined to exceed a second level before the over-erase limit in the erase direction after said first write process is completed,

wherein said first level is closer to said over-erase limit than said second level, and wherein said second level is between said first level and an erase level indicating a limit of the threshold voltage distribution in a counter-erase direction,

wherein said erase process is a process of causing a limit of the threshold voltage distribution in the counter-erase direction to reach an erase limit by repeating an erase verify which determines whether or not the limit of the threshold voltage distribution in the counter-erase direction has reached an erase determination level and erase voltage application which applies an erase voltage when the erase determination level has not been reached,

wherein said first write process brings the limit of the threshold voltage distribution in the erase direction within a range under said first level by repeating a first write verify which determines whether or not the limit of the threshold voltage distribution in the erase direction exceeds said first level and first write voltage application which applies the write voltage when a result of the first write verify indicates the first level is exceeded, and

wherein said control circuit repeats a first loop including said erase voltage application and the first write verify until the limit of the threshold voltage distribution in the erase direction exceeds said first level, then repeats a second loop including said erase voltage application and the erase verify, performs the first write verify partway through said second loop, and inserts the first write voltage application when the limit of the threshold voltage distribution in the erase direction exceeds said first level.

2. The semiconductor integrated circuit according to claim 1,

wherein an application time of one session of erase voltage application in said second loop is longer than an application time of one session of erase voltage application in said first loop.

3. The semiconductor integrated circuit according to claim 2,

wherein the application time of one session of erase voltage application in said second loop corresponds to a cumulative application time of erase voltage application in said first loop.

4. The semiconductor integrated circuit according to claim 3, including:

a memory array in which said plurality of nonvolatile memory cells are connected in parallel to bit lines and source lines to have respective select terminals connected individually to word lines,

wherein a selected one of the word lines is placed on a selected level and an unselected one of the word lines is placed on a non-selected level in a read operation.

5. The semiconductor integrated circuit according to claim 4, including:

a nonvolatile memory comprising said nonvolatile memory cells.

6. The semiconductor integrated circuit according to claim 5, including:

a central processing unit capable of accessing said nonvolatile memory to be constructed as a data processor.

7. The semiconductor integrated circuit according to claim 6,

wherein said control circuit includes said central processing unit and a memory region having an operation program therefor.