Adaptive radio transceiver with filtering

• US 7,233,772 B1
• Filed: 10/19/2000
• Issued: 06/19/2007
• Est. Priority Date: 10/21/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Darabi, Hooman, Khorram, Shahla, Rofougaran, Ahmadreza, Ibrahim, Brima
• Primary Examiner(s): Milord; Marceau
• Application Number:
  US09/692,420
• Time in Patent Office: 2,434 Days
• Field of Search: 455/20, 455/22, 455/23, 455/86, 455/88, 455/190.1, 455/189.1, 455/191.2, 455/80, 455/118, 455/127.1, 455/127.2, 455/260, 455/76, 330/252, 330/257
• US Class Current: 455/20
• CPC Class Codes: H03B 21/01 by beating unmodulated signals of different frequencies
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45386 the AAC comprising one or more coils in the source circuit
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03H 11/126 using a single operational amplifier H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 11/344 : Duplexers
• CPC Class Codes: H03H 2011/0494 : Complex filters
• CPC Class Codes: H03H 21/0001 : Analogue adaptive filters
• CPC Class Codes: H03H 21/0012 : Digital adaptive filters
• CPC Class Codes: H03H 2210/025 : Capacitor
• CPC Class Codes: H03H 2210/036 : Stepwise
• CPC Class Codes: H03H 7/42 : Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 17/104 : of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04B 17/14 : of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/19 : Self-testing arrangements

Abstract

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. A filter circuit, comprising:

a plurality of cascaded filters; and

a bypass circuit coupled across one of the cascaded filters,

wherein the cascaded filters each comprises first and second amplifiers each having a feedback loop comprising a feedback resistor and feedback capacitor coupled in parallel.

2. The filter circuit of claim 1 wherein the bypass circuit comprises a switch.

3. The filter circuit of claim 1 further comprising a plurality of bypass circuits including the bypass circuit, the bypass circuit each being coupled across a different one of the cascaded filters.

4. The filter circuit of claim 3 wherein each of the bypass circuits are adapted for individual control.

5. The filter circuit of claim 3 wherein the bypass circuits each comprises a switch.

6. The filter circuit of claim 1 wherein the cascaded filters each comprises a biquad filter.

7. The filter circuit of claim 1 wherein the cascaded filters each comprises a complex filter.

8. The filter circuit of claim 1 wherein the cascaded filters each comprises a differential filter.

9. The filter circuit of claim 1 wherein the cascaded filters each comprises a pole and a zero.

10. The filter circuit of claim 1 wherein the cascaded filters each comprises a complex filter with a pole and a zero.

11. The filter circuit of claim 1 wherein at least one of the feedback resistors is programmable.

12. The filter circuit of claim 11 wherein said at least one programmable feedback resistor comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

13. The filter circuit of claim 1 wherein at least one of the feedback capacitors is programmable.

14. The filter circuit of claim 13 wherein said at least one programmable feedback capacitor comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

15. The filter circuit of claim 1 wherein the cascaded filters each comprises a first cross coupled resistor coupled between an output of the first amplifier and an input of the second amplifier, and a second cross coupled resistor coupled between an output of the second amplifier and an input of the first amplifier.

16. The filter circuit of claim 15 wherein the cascaded filters each comprises a first input resistor coupled to the input of the first amplifier, and a second input resistor coupled to the input of the second amplifier.

17. The filter circuit of claim 15 wherein the cascaded filters each comprises an input capacitor having one end coupled to the first input resistor and a second end coupled to the second input resistor.

18. The filter circuit of claim 17 wherein at least one of the capacitors is programmable.

19. The filter circuit of claim 18 wherein said at least one programmable capacitor comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

20. The filter circuit of claim 17 wherein at least one the resistor is programmable.

21. The filter circuit of claim 20 wherein said at least one programmable resistors comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

22. The filter circuit according to claim 1, wherein the filter circuit is part of a single integrated circuit chip of a wireless communications device.

23. The filter circuit according to claim 1, wherein the filter circuit is part of an integrated circuit of a receiver in a wireless communications device.

24. The filter circuit according to claim 23, wherein the receiver is part of a single integrated circuit chip transceiver in the wireless communications device.

25. The filter circuit according to claim 1, wherein the filter circuit is part of a single integrated circuit chip transceiver in a wireless communications device.

26. The filter circuit according to claim 1, wherein the filter circuit is part of an integrated circuit chip in a transceiver in a wireless communications device.

27. The filter circuit according to claim 26, wherein the wireless communications device performs orthogonal frequency division multiplexing.

28. The filter circuit according to claim 26, wherein the wireless communications device performs spread spectrum modulation.

29. The filter circuit according to claim 28, wherein the transceiver comprises a single integrated circuit chip transceiver.

30. The filter circuit according to claim 26, wherein the wireless communications device performs frequency hopping.

31. The filter circuit according to claim 26, wherein the wireless communications device performs direct sequence spread spectrum modulation.

32. The filter circuit according to claim 26, wherein the wireless communications device supports communications that use frequency hopping and communications that use direct sequence spread spectrum modulation.

33. The filter circuit according to claim 26, wherein the wireless communications device supports communications that use spread spectrum modulation and communications that use orthogonal frequency division multiplexing.

34. The filter circuit according to claim 26,

wherein the transceiver comprises a single integrated circuit chip transceiver, and

wherein the wireless communications device supports a plurality of different wireless spread spectrum communication techniques.

35. The filter circuit according to claim 34, wherein the wireless communications device performs orthogonal frequency division multiplexing.

36. A filter circuit, comprising:

a plurality of cascaded filters; and

bypass means for bypassing at least one of the cascaded filters,

wherein the cascaded filters each comprises first and second amplifiers each having a feedback loop comprising a feedback resistor and feedback capacitor coupled in parallel.

37. The filter circuit of claim 36 wherein the bypass means comprises a switch coupled across one of the cascaded filters.

38. The filter circuit of claim 36 wherein the bypass means comprises a plurality of switches each being coupled across a different one of the cascaded filters.

39. The filter circuit of claim 36 wherein the switches each comprises means for being individually controlled.

40. The filter circuit of claim 36 wherein the cascaded filters each comprises a biquad filter.

41. The filter circuit of claim 36 wherein the cascaded filters each comprises a complex filter.

42. The filter circuit of claim 36 wherein the cascaded filters each comprises means for generating a pole and zero.

43. The filter circuit of claim 36 wherein the cascaded filters each comprises a complex filter, the complex filters each comprising means for generating a pole and zero.

44. The filter circuit of claim 36 wherein at least one of the feedback resistors comprises means for being programmed to one of a plurality of resistive values.

45. The filter circuit of claim 44 wherein the means for being programmed comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

46. The filter circuit of claim 36 wherein at least one of the feedback capacitors comprises means for being programmed to one of a plurality of capacitive values.

47. The filter circuit of claim 46 wherein the means for being programmed comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

48. The filter circuit of claim 36 wherein the cascaded filters each comprises a first cross coupled resistor coupled between an output of the first amplifier and an input of the second amplifier, and a second cross coupled resistor coupled between an output of the second amplifier and an input of the first amplifier.

49. The filter circuit of claim 48 wherein the cascaded filters each comprises a first input resistor coupled to the input of the first amplifier, and a second input resistor coupled to the input of the second amplifier.

50. The filter circuit of claim 49 wherein the cascaded filters each comprises an input capacitor having one end coupled to the first input resistor and a second end coupled to the second input resistor.

51. The filter circuit of claim 50 wherein at least one of the capacitors comprises means for being programmed to one of a plurality of capacitive values.

52. The filter circuit of claim 51 wherein the means for being programmed comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

53. The filter circuit of claim 50 wherein at least one the resistor comprises means for being programmed to one of a plurality of resistive values.

54. The filter circuit of claim 53 wherein the means for being programmed comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

55. The filter circuit of claim 36 wherein the cascaded filters each comprises a differential filter.

56. The filter circuit according to claim 36, wherein the filter circuit is part of a single integrated circuit chip of a wireless communications device.

57. The filter circuit according to claim 36, wherein the filter circuit is part of an integrated circuit of a receiver in a wireless communications device.

58. The filter circuit according to claim 57, wherein the receiver is part of a single integrated circuit chip transceiver in the wireless communications device.

59. The filter circuit according to claim 36, wherein the filter circuit is part of a single integrated circuit chip transceiver in a wireless communications device.

60. The filter circuit according to claim 36, wherein the filter circuit is part of an integrated circuit chip in a transceiver in a wireless communications device.

61. The filter circuit according to claim 60, wherein the wireless communications device performs orthogonal frequency division multiplexing.

62. The filter circuit according to claim 60, wherein the wireless communications device performs spread spectrum modulation.

63. The filter circuit according to claim 62, wherein the transceiver comprises a single integrated circuit chip transceiver.

64. The filter circuit according to claim 60, wherein the wireless communications device performs frequency hopping.

65. The filter circuit according to claim 60, wherein the wireless communications device performs direct sequence spread spectrum modulation.

66. The filter circuit according to claim 60, wherein the wireless communications device supports communications that use frequency hopping and communications that use direct sequence spread spectrum modulation.

67. The filter circuit according to claim 60, wherein the wireless communications device supports communications that use spread spectrum modulation and communications that use orthogonal frequency division multiplexing.

68. The filter circuit according to claim 60,

wherein the transceiver comprises a single integrated circuit chip transceiver, and

wherein the wireless communications device supports a plurality of different wireless spread spectrum communication techniques.

69. The filter circuit according to claim 68, wherein the wireless communications device performs orthogonal frequency division multiplexing.

70. A filter circuit, comprising:

a biquad filter;

a polyphase filter coupled to the biquad filter; and

a plurality of bypass circuits each being coupled across a different one of the biquad filters,

wherein the biquad filters each comprises first and second amplifiers each having a feedback loop comprising a feedback resistor and feedback capacitor coupled in parallel.

71. The filter circuit of claim 70 further comprising a plurality of biquad filters including the biquad filter, and a plurality of polyphase filters including the polyphase filter, the biquad filters being intertwined with the polyphase filters.

72. The filter circuit of claim 70 wherein each of the bypass circuits are adapted for individual control.

73. The filter circuit of claim 70 wherein the bypass circuits each comprises a switch.

74. The filter circuit of claim 70 wherein the filters each comprises a differential filter.

75. The filter circuit of claim 70 wherein at least one of the feedback resistors is programmable.

76. The filter circuit of claim 75 wherein said at least one programmable feedback resistor comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

77. The filter circuit of claim 70 wherein at least one of the feedback capacitors is programmable.

78. The filter circuit of claim 77 wherein said at least one programmable feedback capacitor comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

79. The filter circuit according to claim 70, wherein the filter circuit is part of a single integrated circuit chip of a wireless communications device.

80. The filter circuit according to claim 70, wherein the filter circuit is part of an integrated circuit of a receiver in a wireless communications device.

81. The filter circuit according to claim 80, wherein the receiver is part of a single integrated circuit chip transceiver in the wireless communications device.

82. The filter circuit according to claim 70, wherein the filter circuit is part of a single integrated circuit chip transceiver in a wireless communications device.

83. The filter circuit according to claim 70, wherein the filter circuit is part of an integrated circuit chip in a transceiver in a wireless communications device.

84. The filter circuit according to claim 83, wherein the wireless communications device performs orthogonal frequency division multiplexing.

85. The filter circuit according to claim 83, wherein the wireless communications device performs spread spectrum modulation.

86. The filter circuit according to claim 85, wherein the transceiver comprises a single integrated circuit chip transceiver.

87. The filter circuit according to claim 83, wherein the wireless communications device performs frequency hopping.

88. The filter circuit according to claim 83, wherein the wireless communications device performs direct sequence spread spectrum modulation.

89. The filter circuit according to claim 83, wherein the wireless communications device supports communications that use frequency hopping and communications that use direct sequence spread spectrum modulation.

90. The filter circuit according to claim 83, wherein the wireless communications device supports communications that use spread spectrum modulation and communications that use orthogonal frequency division multiplexing.

91. The filter circuit according to claim 83,

wherein the transceiver comprises a single integrated circuit chip transceiver, and

wherein the wireless communications device supports a plurality of different wireless spread spectrum communication techniques.

92. The filter circuit according to claim 91, wherein the wireless communications device performs orthogonal frequency division multiplexing.

93. A filter circuit, comprising:

a biquad filter; and

a polyphase filter coupled to the biquad filter,

wherein the biquad filters each comprises a first cross coupled resistor coupled between an output of the first amplifier and an input of the second amplifier, and a second cross coupled resistor coupled between an output of the second amplifier and an input of the first amplifier.

94. The filter circuit of claim 93 wherein the biquad filters each comprises a first input resistor coupled to the input of the first amplifier, and a second input resistor coupled to the input of the second amplifier.

95. The filter circuit of claim 94 wherein the biquad filters each comprises an input capacitor having one end coupled to the first input resistor and a second end coupled to the second input resistor.

96. The filter circuit of claim 95 wherein at least one of the capacitors is programmable.

97. The filter circuit of claim 96 wherein said at least one programmable capacitor comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

98. The filter circuit of claim 95 wherein at least one the resistor is programmable.

99. The filter circuit of claim 98 wherein said at least one programmable resistors comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

100. The filter circuit according to claim 93, wherein the filter circuit is part of a single integrated circuit chip of a wireless communications device.

101. The filter circuit according to claim 93, wherein the filter circuit is part of an integrated circuit of a receiver in a wireless communications device.

102. The filter circuit according to claim 101, wherein the receiver is part of a single integrated circuit chip transceiver in the wireless communications device.

103. The filter circuit according to claim 93, wherein the filter circuit is part of a single integrated circuit chip transceiver in a wireless communications device.

104. The filter circuit according to claim 93, wherein the filter circuit is part of an integrated circuit chip in a transceiver in a wireless communications device.

105. The filter circuit according to claim 104, wherein the wireless communications device performs orthogonal frequency division multiplexing.

106. The filter circuit according to claim 104, wherein the wireless communications device performs spread spectrum modulation.

107. The filter circuit according to claim 106, wherein the transceiver comprises a single integrated circuit chip transceiver.

108. The filter circuit according to claim 104, wherein the wireless communications device performs frequency hopping.

109. The filter circuit according to claim 104, wherein the wireless communications device performs direct sequence spread spectrum modulation.

110. The filter circuit according to claim 104, wherein the wireless communications device supports communications that use frequency hopping and communications that use direct sequence spread spectrum modulation.

111. The filter circuit according to claim 104, wherein the wireless communications device supports communications that use spread spectrum modulation and communications that use orthogonal frequency division multiplexing.

112. The filter circuit according to claim 104,

wherein the transceiver comprises a single integrated circuit chip transceiver, and

wherein the wireless communications device supports a plurality of different wireless spread spectrum communication techniques.

113. The filter circuit according to claim 112, wherein the wireless communications device performs orthogonal frequency division multiplexing.

114. A complex differential filter, comprising:

first and second differential amplifiers each having a differential input and a differential output;

a first input resistor coupled to a first one of the differential inputs of the first differential amplifier;

a second input resistor coupled to a second one of the differential inputs of the first differential amplifier;

a third input resistor coupled to a first one of the differential inputs of the second differential amplifier;

a fourth input resistor coupled to a second one of the differential inputs of the second differential amplifier;

a first input capacitor having one end coupled to the first input resistor and another end coupled to the third input resistor;

a second input capacitor having one end coupled to the second input resistor and another end coupled to the fourth input resistor;

a third input capacitor having one end coupled to the third input resistor and another end coupled to the second input resistor; and

a fourth input capacitor having one end coupled to the fourth input resistor and another end coupled to the first input resistor.

115. The complex differential filter of claim 114 wherein at least one of the input resistors is programmable.

116. The complex differential filter of claim 115 wherein said at least one programmable input resistor comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

117. The complex differential filter of claim 114 wherein at least one of the input capacitors is programmable.

118. The complex differential filter of claim 117 wherein said at least one programmable input capacitor comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

119. The complex differential filter of claim 114 wherein the first and second differential amplifiers each comprises a feedback loop comprising a feedback resistor and feedback capacitor coupled in parallel.

120. The complex differential filter of claim 114 wherein the first differential amplifier comprises a first feedback loop coupled between a first one of its differential outputs and the first one of its differential inputs, and a second feedback loop coupled between a second one of its differential outputs and the second one of its differential inputs, the feedback loops each comprising a feedback resistor and feedback capacitor coupled in parallel.

121. The complex differential filter of claim 120 wherein the second differential amplifier comprises a third feedback loop coupled between a first one of its differential outputs and the first one of its differential inputs, and a second feedback loop coupled between a second one of its differential outputs and the second one of its differential inputs, the third and fourth feedback loops each comprising a feedback resistor and feedback capacitor coupled in parallel.

122. The complex differential filter of claim 121 further comprising a first cross coupled resistor coupled between the first one of the differential outputs of the first differential amplifier and the second one of the differential inputs of the second differential amplifier, a second cross coupled resistor coupled between a second one of the differential outputs of the first differential amplifier and the first one of the differential inputs of the second differential amplifier, a third cross coupled resistor coupled between the first one of the differential outputs of the second differential amplifier and the first one of the differential inputs of the first differential amplifier, and a fourth cross coupled resistor coupled between a second one of the differential outputs of the second differential amplifier and the second one of the differential inputs of the first differential amplifier.

123. The complex differential filter of claim 122 wherein at least one of the capacitors is programmable.

124. The complex differential filter of claim 123 wherein said at least one programmable capacitor comprises a plurality of capacitors coupled in parallel, said plurality of capacitors each having a switch coupled thereacross.

125. The complex differential filter of claim 122 wherein at least one the resistor is programmable.

126. The complex filter of claim 125 wherein said at least one programmable resistors comprises a plurality of resistors coupled in series, said plurality of resistors each having a switch coupled thereacross.

127. The complex differential filter according to claim 114, wherein the complex differential filter is part of a single integrated circuit chip of a wireless communications device.

128. The complex differential filter according to claim 114, wherein the complex differential filter is part of an integrated circuit of a receiver in a wireless communications device.

129. The complex differential filter according to claim 128, wherein the receiver is part of a single integrated circuit chip transceiver in the wireless communications device.

130. The complex differential filter according to claim 114, wherein the complex differential filter is part of a single integrated circuit chip transceiver in a wireless communications device.

131. The complex differential filter according to claim 114, wherein the complex differential filter is part of an integrated circuit chip in a transceiver in a wireless communications device.

132. The complex differential filter according to claim 131, wherein the wireless communications device performs orthogonal frequency division multiplexing.

133. The complex differential filter according to claim 131, wherein the wireless communications device performs spread spectrum modulation.

134. The complex differential filter according to claim 133, wherein the transceiver comprises a single integrated circuit chip transceiver.

135. The complex differential filter according to claim 131, wherein the wireless communications device performs frequency hopping.

136. The complex differential filter according to claim 131, wherein the wireless communications device performs direct sequence spread spectrum modulation.

137. The complex differential filter according to claim 131, wherein the wireless communications device supports communications that use frequency hopping and communications that use direct sequence spread spectrum modulation.

138. The complex differential filter according to claim 131, wherein the wireless communications device supports communications that use spread spectrum modulation and communications that use orthogonal frequency division multiplexing.

139. The complex differential filter according to claim 131,

wherein the transceiver comprises a single integrated circuit chip transceiver, and

wherein the wireless communications device supports a plurality of different wireless spread spectrum communication techniques.

140. The complex differential filter according to claim 139, wherein the wireless communications device performs orthogonal frequency division multiplexing.

141. A method of complex filtering to extract a signal in a frequency spectrum comprising a plurality of channels, comprising:

selecting one of the channels having the signal;

rejecting an image of the signal in the selected channel; and

applying gain to the signal, the applied gain being programmable,

wherein the channel selection comprises programming an order of complex filtering.

142. The method of claim 141 wherein the channel selection comprises tuning a center frequency of the channel.

143. The method of claim 142 wherein the channel selection further comprises tuning a bandwidth of the channel.

144. The method of claim 141 further comprising introducing a zero to filter a frequency in the selected channel different from a frequency of the signal.

145. The method of claim 141 further comprising introducing a plurality of zeros each filtering a different frequency in the selected channel, the filtered frequencies each being different from a frequency of the signal.

146. The method of claim 145 further wherein the introducing of the zeros comprises programming the number of the zeros introduced.

147. The method according to claim 141, wherein the method is performed by a single integrated circuit chip of a wireless communications device.

148. The method according to claim 141, wherein the method is performed by an integrated circuit of a receiver in a wireless communications device.

149. The method according to claim 148, wherein the receiver is part of a single integrated circuit chip transceiver in the wireless communications device.

150. The method according to claim 141, wherein the method is performed by a single integrated circuit chip transceiver in a wireless communications device.

151. The method according to claim 141, wherein the method is performed by an integrated circuit chip in a transceiver in a wireless communications device.

152. The method according to claim 151, wherein the wireless communications device performs orthogonal frequency division multiplexing.

153. The method according to claim 151, wherein the wireless communications device performs spread spectrum modulation.

154. The method according to claim 153, wherein the transceiver comprises a single integrated circuit chip transceiver.

155. The method according to claim 151, wherein the wireless communications device performs frequency hopping.

156. The method according to claim 151, wherein the wireless communications device performs direct sequence spread spectrum modulation.

157. The method according to claim 151, wherein the wireless communications device supports communications that use frequency hopping and communications that use direct sequence spread spectrum modulation.

158. The method according to claim 151, wherein the wireless communications device supports communications that use spread spectrum modulation and communications that use orthogonal frequency division multiplexing.

159. The method according to claim 151,

wherein the transceiver comprises a single integrated circuit chip transceiver, and

wherein the wireless communications device supports a plurality of different wireless spread spectrum communication techniques.

160. The method according to claim 159, wherein the wireless communications device performs orthogonal frequency division multiplexing.