Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device

• US 7,233,889 B2
• Filed: 10/23/2002
• Issued: 06/19/2007
• Est. Priority Date: 10/25/2001
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Saito, Yoshiyuki, Takahashi, Eiji, Benno, Hiroshi, Fukumoto, Yukihiro
• Primary Examiner(s): Rodriguez; Paul
• Assistant Examiner(s): PIERRE LOUIS, ANDRE
• Application Number:
  US10/278,507
• Publication Number:
  US 20030083857A1
• Time in Patent Office: 1,700 Days
• Field of Search: 703/14, 324/750, 324/765, 324/762, 324/613
• US Class Current: 703/14
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.

Claims

1. A noise immunity evaluation design apparatus for evaluating noise immunity using a software simulation that represents a design of a circuit for a semiconductor device comprising:

an acquiring unit, acquiring the software simulation, the software simulation including a simulated external noise source, a simulated external circuit, an impedance of a design power supplying circuit, an impedance of a design logic circuit, and an impedance of a design grounding circuit, the noise immunity evaluation apparatus further comprising;

a specifying unit, specifying a first frequency of a voltage generated by the noise source;

a calculating unit, calculating a first voltage directly across the design logic circuit impedance when a voltage of the specified first frequency is applied;

an outputting unit, outputting the specified first frequency and the calculated first voltage; and

an evaluation unit operable to output an evaluation of the noise immunity of the simulation circuit model, for the first frequency of a voltage generated by the noise source in comparison with a predetermined tolerance level for external noise where the evaluation is utilized to modify at least one of the impedances until the calculated first voltage falls within the predetermined tolerance level.

2. The noise immunity evaluation design apparatus of claim 1,

wherein the power supplying circuit, the logic circuit, and the grounding circuit of the software simulation are connected in series with each other and form a simulated internal circuit, and the simulated internal circuit is connected in parallel with the simulated external noise source,

the simulated external circuit, the simulated internal circuit, and the simulated noise source are connected in parallel with each other, and

the calculating unit calculates the first voltage further using an impedance of the simulated external circuit.

3. The noise immunity evaluation design apparatus of claim 1,

wherein the power supplying circuit, the logic circuit, and the grounding circuit form a simulated internal circuit, and are each made up of a plurality of circuit blocks,

a circuit block of the power supplying circuit, a circuit block of the logic circuit, and a circuit block of the grounding circuit are connected in series with each other, and are respectively connected in parallel with a remaining circuit block of the power supplying circuit, a remaining circuit block of the logic circuit, and a remaining circuit block of the grounding circuit, and

the calculating unit calculates a voltage arising directly across each circuit block of the logic circuit.

4. The noise immunity evaluation design apparatus of claim 3,

wherein the external circuit, the internal circuit, and the noise source are connected in parallel with each other, and

the calculating unit calculates voltage arising directly across each circuit block of the logic circuit, further using an impedance of the external circuit.

13. The noise immunity evaluation design apparatus of claim 1 wherein the evaluation unit utilizes a difference in one of an absolute value and phase of the voltages and currents between the respective circuits.

5. A noise immunity evaluation method used in a noise immunity evaluation apparatus for evaluating noise immunity using a computer generated simulation model, the simulation model including a noise source, an impedance of a power supplying circuit, an impedance of a logic circuit, and an impedance of a grounding circuit, the noise immunity evaluation method comprising:

a specifying step of specifying a frequency of a voltage generated by the noise source;

a calculating step of calculating a first voltage arising directly across the logic circuit impedance when a voltage of the specified frequency is applied;

an outputting step of outputting the specified frequency and the calculated first voltage, and

an evaluation step to compare the specified frequency and the calculated first voltage with a predetermined tolerance level for external noise and output an indication whether the calculated first voltage falls within the tolerance level.

6. The noise immunity evaluation method of claim 5,

wherein the power supplying circuit, the logic circuit, and the grounding circuit are connected in series with each other and form a simulated internal circuit, and

the simulated internal circuit is connected in parallel with the noise source,

the simulation model further includes a simulated external circuit which is provided outside the simulated internal circuit,

the simulated external circuit, the simulated internal circuit, and the noise source are connected in parallel with each other, and

the calculating step calculates the first voltage further using an impedance of the simulated external circuit.

7. The noise immunity evaluation method of claim 5,

wherein the power supplying circuit, the logic circuit, and the grounding circuit form a simulated internal circuit, and are each made up of a plurality of circuit blocks,

a circuit block of the power supplying circuit, a circuit block of the logic circuit, and a circuit block of the grounding circuit are connected in series with each other, and are respectively connected in parallel with a remaining circuit block of the power supplying circuit, a remaining circuit block of the logic circuit, and a remaining circuit block of the grounding circuit, and

the calculating step calculates voltage arising directly across each circuit block of the logic circuit.

8. The noise immunity evaluation method of claim 7,

wherein the simulation model further includes a simulated external circuit which is provided outside the simulated internal circuit,

the simulated external circuit, the simulated internal circuit, and the noise source are connected in parallel with each other, and

the calculating step calculates voltage arising directly across each circuit block of the logic circuit, further using an impedance of the simulated external circuit.

14. The noise immunity evaluation method of claim 5 further including a step of altering one or more of the impedances of the respective power supplying circuit, logic circuit and ground current and repeating the specifying step, calculating step, outputting step and evaluation step until the computer generated simulation model is within the predetermined tolerance level for external noise.

9. A program recording medium which is readable by a computer in a noise immunity evaluation apparatus for evaluating noise immunity using a simulation model, the simulation model including a noise source, an impedance of a power supplying circuit, an impedance of a logic circuit, and an impedance of a grounding circuit, wherein a computer program embodied on the program recording medium has the computer conduct:

a specifing step of specifying a frequency of a voltage generated by the noise source;

a calculating step of calculating a first voltage directly across the logic circuit impedance when a voltage of the specified frequency is applied; and

an outputting step of outputting the specified frequency and the calculated first voltage.

10. The program recording medium of claim 9,

wherein the power supplying circuit, the logic circuit, and the grounding circuit are connected in series with each other and form a simulated internal circuit, and the simulated internal circuit is connected in parallel with the noise source,

the simulation model further includes a simulated external circuit which is provided outside the simulated internal circuit,

the simulated external circuit, the simulated internal circuit, and the noise source are connected in parallel with each other, and

the calculating step calculates the first voltage further using an impedance of the external circuit.

11. The program recording medium of claim 9,

wherein the power supplying circuit, the logic circuit, and the grounding circuit form a simulated internal circuit, and are each made up of a plurality of circuit blocks,

a circuit block of the power supplying circuit, a circuit block of the logic circuit, and a circuit block of the grounding circuit are connected in series with each other, and are respectively connected in parallel with a remaining circuit block of the power supplying circuit, a remaining circuit block of the logic circuit, and a remaining circuit block of the grounding circuit, and

the calculating step calculates a voltage arising directly across each circuit block of the logic circuit.

12. The program recording medium of claim 11,

wherein the simulation model further includes a simulated external circuit which is provided outside the simulated internal circuit,

the simulated external circuit, the simulated internal circuit, and the noise source are connected in parallel with each other, and

the calculating step calculates voltage arising directly across each circuit block of the logic circuit, further using an impedance of the simulated external circuit.

15. The program recording medium of claim 9 further including a step of altering one or more of the impedances of the respective power supplying circuit, logic circuit and ground current and repeating the specifying step, calculating step, outputting step and evaluation step until the calculated first voltage lies within a predetermined tolerance level for external noise.