Computational method, system, and apparatus
First Claim
1. An apparatus for performing exponentiations, comprising:
- a set of computational devices containing first and second subsets, wherein the first subset has a plurality of members which are chained together such that the devices of the first subset can operate both independently and as members of a first computational chain, and wherein the second subset has a plurality of members which are chained together such that the devices of the second subset can operate both independently and as members of a second computational chain distinct from said first computational chain; and
a chaining controller adapted to instruct the first subset of devices to act as a first computational chain when the apparatus is required to perform an exponentiation of a first size, and being further adapted to instruct the second subset of devices to act as a second computational chain when the apparatus is required to perform an exponentiation of a second size distinct from said first size;
wherein each computational device is adapted to perform 1024-bit exponentiation, wherein said chaining controller is adapted to instruct the first subset of devices to act as a first computational chain when the apparatus is required to perform 2048-bit exponentiation, and wherein said chaining controller is adapted to instruct the second subset of devices to act as a second computational chain when the apparatus is required to perform 4096-bit exponentiation.
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Abstract
A method, system, and apparatus for performing computations.
In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory.
A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations.
An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.
86 Citations
42 Claims
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1. An apparatus for performing exponentiations, comprising:
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a set of computational devices containing first and second subsets, wherein the first subset has a plurality of members which are chained together such that the devices of the first subset can operate both independently and as members of a first computational chain, and wherein the second subset has a plurality of members which are chained together such that the devices of the second subset can operate both independently and as members of a second computational chain distinct from said first computational chain; and a chaining controller adapted to instruct the first subset of devices to act as a first computational chain when the apparatus is required to perform an exponentiation of a first size, and being further adapted to instruct the second subset of devices to act as a second computational chain when the apparatus is required to perform an exponentiation of a second size distinct from said first size; wherein each computational device is adapted to perform 1024-bit exponentiation, wherein said chaining controller is adapted to instruct the first subset of devices to act as a first computational chain when the apparatus is required to perform 2048-bit exponentiation, and wherein said chaining controller is adapted to instruct the second subset of devices to act as a second computational chain when the apparatus is required to perform 4096-bit exponentiation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for encrypting/decrypting data comprising:
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providing a 1024-bit number X; and encrypting/decrypting X by loading X into session memory, cleaving X mod P to compute XP, cleaving X mod Q to compute XQ, exponentiating Xp to compute CP, exponentiating XQ to compute CQ, merging CP and CQ to compute C, wherein C is a 1024-bit number, and retrieving C from the session memory; wherein the method further comprises (a) selecting one of a plurality of session controllers;
(b) setting the busy bit for the one session controller; and
(c) clearing the busy bit for the one session controller. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A device for performing computations, comprising:
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a plurality of exponentiators; and a chaining controller adapted to arrange a first group of said exponentiators into a first computational chain when the device is required to process exponentiations of a first size, and being further adapted to arrange a second group of said exponentiators into a second computational chain when the device is required to process exponentiations of a second size distinct from said first size; wherein the memories of said plurality of exponentiators map into a single global address. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A device for performing computations, comprising:
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a plurality of exponentiators, wherein each of said plurality of exponentiators is adapted to simultaneously process eight 1K exponentiations, four 2K exponentiations, or two 8K exponentiations; and a chaining controller adapted to arrange a first group of said exponentiators into a first computational chain when the device is required to process exponentiations of a first size, and being further adapted to arrange a second group of said exponentiators into a second computational chain when the device is required to process exponentiations of a second size distinct from said first size.
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42. A device for performing computations, comprising:
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a plurality of exponentiators; and a chaining controller adapted to arrange a first group of said exponentiators into a first computational chain when the device is required to process exponentiations of a first size, and being further adapted to arrange a second group of said exponentiators into a second computational chain when the device is required to process exponentiations of a second size distinct from said first size; wherein said chaining controller is a direct memory access controller which is adapted to load arguments and control information into the internal memory and registers of said plurality of exponentiators, wherein each of said plurality of exponentiators comprises a plurality of session controllers, and wherein each of said plurality of session controllers is adapted to process separate exponentiations concurrently.
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Specification