Method and apparatus for accessing management information base data

• US 7,233,986 B1
• Filed: 09/20/2002
• Issued: 06/19/2007
• Est. Priority Date: 08/14/2002
• Status: Active Grant

• Current Assignee: Ericsson AB (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Redback Networks Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Jair, Hsinlun, Mangin, Jim
• Primary Examiner(s): Wiley; David
• Assistant Examiner(s): Nguyen; Phuoc H
• Application Number:
  US10/251,504
• Time in Patent Office: 1,733 Days
• Field of Search: 709/212, 709/223, 709/226, 711/3, 711/100, 711/170
• US Class Current: 709/223
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]

Abstract

A method and apparatus for accessing management information base data is described. A method in a network element comprises collecting a first set of management information base (MIB) data in a framer'"'"'s memory, maintaining a second set of MIB data that is periodically updated with the first set of MIB data, wherein the second set of MIB data is maintained separately from the first set of MIB data; and, in response to a request for the MIB data, transmitting the second set of MIB data.

Claims

1. A method in a network element comprising:

collecting a first set of management information base (MIB) data by a first processing circuit in a framer into a framer'"'"'s memory, the first processing circuit to perform framing operations;

maintaining by a second processing circuit a second set of MIB data that is periodically updated with the first set of MIB data by the second processing circuit, wherein the second set of MIB data is maintained separately from the first set of MIB data, and the second processing circuit is separate from the first processing circuit; and

in response to a request for the MIB data, transmitting the second set of MIB data by the second processing circuit, and

wherein the first set of MIB data is maintained by the first processing circuit of the framer while the second set of MIB data is maintained by the second processing circuit, the second processing circuit being a field programmable gate array.

2. The method of claim 1 wherein collecting comprises gathering statistical information about traffic traversing the network element.

3. The method of claim 1 wherein transmitting the second set of MIB data comprises direct memory access (DMA) writing the second set of MIB data.

4. The method of claim 1 further comprising writing a set of one or more tag bits at the end of the transmitted second set of MIB data, said set of tag bits indicating the end of the second set of MIB data.

5. The method of claim 1 further comprising:

collecting a third set of MIB data in the framer'"'"'s memory;

in response to a request, collecting the third set of MIB data into a second memory; and

transmitting the collected third set of MIB data from the second memory across a bus to a third memory.

6. The method of claim 1 wherein the transmitting comprises packetizing the second set of MIB data.

7. A method in a network element comprising:

in response to a request for management information base (MIB) data, accessing a first set of MIB data that is maintained by a field programmable gate array (FPGA),

wherein the MIB data is separate from a second set of MIB data that is used by the FPGA to periodically update the first set of MIB data;

collecting the second set of MIB data by a framer into a framer'"'"'s memory, the framer separate from the FPGA, the framer to perform framing operations and maintain the second set of MIB data; and

direct memory access writing the first set of MIB data into a memory on a forwarding engine card by the FPGA.

8. The method of claim 7 further comprising packeting the first set of MIB data.

9. The method of claim 7 wherein the request is a write request from the forwarding engine card.

10. The method of claim 7 further comprising:

transmitting the first set of MIB data to a control engine from the memory on the forwarding engine card.

11. The method of claim 7 further comprising:

in response to a request from a control engine, communicating to the control engine the first set of MIB data'"'"'s location in the memory on the forwarding engine card.

12. A method in a network element comprising:

maintaining a first and second set of management information base (MIB) data in separate memory locations, wherein the first set of MIB data is based on received packets processed by a first circuit and the second set of MIB data is maintained by a second circuit based on the first set of MIB data;

accessing the second set of MIB data by the second circuit in response to a request for MIB data;

creating a set of one or more packets by the second circuit based on the second set of MIB data; and

direct memory access writing the set of packets by the second circuit across a bus into memory on a forwarding engine card

wherein the first circuit maintains the first set of MIB data and the second circuit maintains the second set of MIB data,

wherein the first circuit is a processing circuit of a framer and the second circuit is a field programmable gate array (FPGA) separate from the first circuit, and

wherein the second MIB is periodically updated with the first MIB data.

13. The method of claim 12 wherein the request is a write request from the forwarding engine card transmitted to the FPGA, the write request being transmitted in response to a request from a control engine.

14. The method of claim 12 wherein the request is provided in response to a time period expiring.

15. The method of claim 12 further comprising providing the second set of MIB data from the memory to a control engine.

16. The method of claim 15 wherein providing the second set of MIB data comprises communicating to the control engine the location in the memory of the second set of MIB data.

17. The method of claim 15 wherein the providing comprises packetizing the second set of MIB data written into the memory and transmitting the packetized second set of MIB data from the memory to the control engine.

18. A network element comprising:

a bus;

a forwarding engine (FE) card coupled with the bus, the FE card to forward packets, the FE card including,

a packet processing module (PPM) to process packets and having a set of instructions to cause the PPM to post a write request for a management information base (MIB),

a bridge coupled with the PPM and the bus, the bridge to transmit requests across the bus and to receive data from the bus,

a memory coupled with the PPM, the memory to host the MIB; and

an input/output (I/O) card coupled with the bus, the I/O card to receive and transmit packets and including,

a framer to collect and maintain MIB data;

an ingress field programmable gate array (iFPGA) coupled with and separate from the framer, the iFPGA to collect and maintain a copy of the MIB data, to periodically update its MIB data with the framer'"'"'s MIB data and to service the write request from the PPM.

19. The network element of claim 18 wherein the forwarding engine card further includes:

a set of one or more gearboxes;

a transmit field FPGA; and

a receive FPGA.

20. The network element of claim 18 wherein the I/O card further includes:

an egress FPGA (eFPGA) coupled with the framer and the bus, the eFPGA to pass packets from the forwarding engine card to the framer;

a first packet memory coupled with the iFPGA;

a first packet descriptor memory coupled with the iFPGA;

a second packet memory coupled with the eFPGA; and

a second packet descriptor memory coupled with the eFPGA.

21. The network element of claim 18 wherein the iFPGA includes a set of one or more registers to host the MIB data.

22. The network element of claim 18 wherein the iFPGA includes:

a PL3 controller;

a packet parser coupled with the PL3 controller;

a packet memory controller coupled with the PL3 controller and the first packet memory;

a descriptor memory controller coupled with the first descriptor memory;

a data mover coupled with the packet memory controller;

a bus controller coupled with the data mover, the bus controller including a first in first out buffer; and

a framer interface coupled with the bus controller and the framer.

23. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:

posting a write request for a first set of management information base (MIB) data;

communicating the write request to a field programmable gate array (FPGA) that maintains the first set of MIB data based on a second set of MIB data maintained by a framer circuit separate from the FPGA; and

direct memory access writing the set of MIB data to a memory on a forwarding engine card,

wherein the first set of MIB data is periodically updated from the second set of MIB data, and

wherein the FPGA collects the first set of data and the framer circuit collects the second set of data.

24. The machine-readable medium of claim 23 wherein the write request is in response to a time period expiring.

25. The machine-readable medium of claim 23 wherein the write request is in response to receiving a MIB request from a control engine.

26. The machine-readable medium of claim 23 further comprising packetizing the set of MIB data for writing to the memory.

27. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:

collecting a first set of management information base (MIB) data by a first processing circuit in a framer'"'"'s memory, the first processing circuit to perform framing operations;

maintaining by a second processing circuit a second set of MIB data that is periodically updated with the first set of MIB data by the second processing circuit, wherein the second set of MIB data is maintained separately from the first set of MIB data, and the second processing circuit is separate from the first processing circuit;

in response to a request for the MIB data, transmitting the second set of MIB data by the second processing circuit,

wherein the first set of MIB data is maintained by the framer while the second set of MIB data is collected by the second processing circuit, the processing circuit being a field programmable gate array.

28. The machine-readable storage medium of claim 27 wherein collecting comprises gathering statistical information about traffic traversing the network element.

29. The machine-readable storage medium of claim 27 wherein transmitting the second set of MIB data comprises direct memory access (DMA) writing the second set of MIB data.

30. The machine-readable storage medium of claim 27 further comprising writing a set of one or more tag bits at the end of the transmitted second set of MIB data, said set of tag bits indicating the end of the second set of MIB data.

31. The machine-readable storage medium of claim 27 further comprising:

collecting a third set of MIB data in the framer'"'"'s memory;

in response to a request, collecting the third set of MIB data into a second memory; and

transmitting the collected third set of MIB data from the second memory across a bus to a third memory.

32. The machine-readable storage medium of claim 27 wherein the transmitting comprises packetizing the second set of MIB data.

33. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:

in response to a request for management information base (MIB) data, accessing a first set of MIB data that is collected and maintained by a field programmable gate array (FPGA), wherein the MIB data is separate from a second set of MIB data that is used by the FPGA to periodically update the first set of MIB data;

collecting the second set of MIB data by a framer into a framer'"'"'s memory, the framer separate from the FPGA, the framer to perform framing operations and maintain the second set of MIB data; and

direct memory access writing the first set of MIB data into a memory on a forwarding engine card by the FPGA.

34. The machine-readable storage medium of claim 33 further comprising packeting the first set of MIB data.

35. The machine-readable storage medium of claim 33 wherein the request is a write request from the forwarding engine card.

36. The machine-readable storage medium of claim 33 further comprising:

transmitting the first set of MIB data to a control engine from the memory on the forwarding engine card.

37. The machine-readable storage medium of claim 33 further comprising:

in response to a request from a control engine, communicating to the control engine the first set of MIB data'"'"'s location in the memory on the forwarding engine card.

38. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:

maintaining a first and second set of management information base (MIB) data in separate memory locations, wherein the first set of MIB data is based on received packets processed by a first circuit and the second set of MIB data is maintained by a second circuit based on the first set of MIB data;

accessing the second set of MIB data by the second circuit in response to a request for MIB data;

creating a set of one or more packets by the second circuit based on the second set of MIB data; and

direct memory access writing the set of packets by the second circuit across a bus into memory on a forwarding engine card

wherein the first circuit collects and maintains the first set of MIB data and the second circuit collects and maintains the second set of MIB data,

wherein the first circuit is a processing circuit of a framer and the second circuit is a field programmable gate array (FPGA) separate from the framer, and

wherein the second MIB is periodically updated with the first MIB data.

39. The machine-readable storage medium of claim 38 wherein the request is a write request from the forwarding engine card transmitted to the FPGA, the write request being transmitted in response to a request from a control engine.

40. The machine-readable storage medium of claim 38 wherein the request is provided in response to a time period expiring.

41. The machine-readable storage medium of claim 38 further comprising providing the second set of MIB data from the memory to a control engine.

42. The machine-readable storage medium of claim 41 wherein providing the second set of MIB data comprises communicating to the control engine the location of the second set of MIB data.

43. The machine-readable storage medium of claim 41 wherein the providing comprises packetizing the second set of MIB data written into the memory and transmitting the packetized second set of MIB data from the memory to the control engine.