Computer architecture and software cells for broadband networks
First Claim
1. A computer network comprising:
- a plurality of processors connected to said network, each of said processors comprising a plurality of first processing units having the same instruction set architecture and a second processing unit for controlling said first processing units, said first processing units being operable to process software cells transmitted over said network, each of said software cells comprising a program compatible with said instruction set architecture, data associated with said program, information for routing said software cell over said network, and an identification number uniquely identifying said software cell among all of said software cells being transmitted over said network, wherein each said processor further includes a main memory, said main memory including a plurality of banks, each said bank including a plurality of blocks, each said block being the lowest addressable unit of said main memory and having an associated memory space in said main memory for storing information regarding the status of data stored in said block, an identification for a first processing unit and an address of a local memory associated with said first processing unit.
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Accused Products
Abstract
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
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Citations
19 Claims
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1. A computer network comprising:
a plurality of processors connected to said network, each of said processors comprising a plurality of first processing units having the same instruction set architecture and a second processing unit for controlling said first processing units, said first processing units being operable to process software cells transmitted over said network, each of said software cells comprising a program compatible with said instruction set architecture, data associated with said program, information for routing said software cell over said network, and an identification number uniquely identifying said software cell among all of said software cells being transmitted over said network, wherein each said processor further includes a main memory, said main memory including a plurality of banks, each said bank including a plurality of blocks, each said block being the lowest addressable unit of said main memory and having an associated memory space in said main memory for storing information regarding the status of data stored in said block, an identification for a first processing unit and an address of a local memory associated with said first processing unit.
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2. A method for processing programs and data associated with said programs on a computer processor, said computer processor comprising a main memory, a memory controller, a plurality of first processing units, each said first processing unit including a local memory exclusively associated with said first processing unit, and a second processing unit, said method comprising:
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storing in said main memory said programs and said data associated with said programs; directing with said second processing unit any one of said first processing units to process one of said programs; directing with said second processing unit said memory controller to transfer said one program and data associated with said one program from said main memory to the local memory exclusively associated with said one first processing unit; instructing with said second processing unit said one first processing unit to initiate processing of said one program from said one first processing unit'"'"'s local memory; and in response to said instructing, processing with said one first processing unit said one program and said data associated with said one program from said local memory exclusively associated with said one first processing unit. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification