Layered crossbar for interconnection of multiple processors and shared memories
First Claim
1. An apparatus comprising:
- a first processor switch comprising a plurality of processors and a processor crossbar, each processor coupled to the processor crossbar; and
a plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch, and each memory crossbar in each of the memory switches coupling to the processor crossbar,wherein a first integrated circuit comprises the processor switch and a second integrated circuit comprises at least one of the memory switches.
7 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.
-
Citations
18 Claims
-
1. An apparatus comprising:
-
a first processor switch comprising a plurality of processors and a processor crossbar, each processor coupled to the processor crossbar; and a plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch, and each memory crossbar in each of the memory switches coupling to the processor crossbar, wherein a first integrated circuit comprises the processor switch and a second integrated circuit comprises at least one of the memory switches. - View Dependent Claims (2, 3, 4)
-
-
5. A method comprising:
-
implementing a first processor switch comprising a plurality of processors and a processor crossbar, each processor coupled to the processor crossbar; implementing a plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch, and each memory crossbar in each of the memory switches coupling to the processor crossbar; and connecting the processor crossbar with each memory crossbar of each memory switch.
-
-
6. An apparatus comprising:
-
a plurality of processor switches, wherein each processor switch comprises; a plurality of processors; and a processor crossbar, wherein each processor in a processor switch is coupled to the processor crossbar of the processor switch; a first plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch; and a first-level intermediate switch comprising a switch crossbar, wherein the switch crossbar is coupled to the processor crossbars and the memory crossbars, wherein a first integrated circuit comprises the processor switches and a second integrated circuit comprises the memory switches. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
-
Specification