Overlapping jumping window for SONET/SDH bit error rate monitoring

• US 7,234,086 B1
• Filed: 01/13/2004
• Issued: 06/19/2007
• Est. Priority Date: 01/16/2003
• Status: Expired due to Fees

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: de Koos, Andras, Youssef, Mounir
• Primary Examiner(s): Lamarre; Guy
• Assistant Examiner(s): Rizk; Sam
• Application Number:
  US10/755,403
• Time in Patent Office: 1,253 Days
• Field of Search: 398/27, 370/333
• US Class Current: 714/704
• CPC Class Codes: H04J 2203/006 Fault tolerance and recovery
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 1/24 Testing correct operation
• CPC Class Codes: H04L 41/0681 Configuration of triggering conditions
• CPC Class Codes: H04L 43/0847 Transmission error
• CPC Class Codes: H04L 43/16 Threshold monitoring

Abstract

A method of performing multiple parallel event accumulations. This method permits devices to implement SONET/SDH Bit Error Rate monitoring on a large number of paths, but at a significantly lower cost of implementation than would be possible using existing approaches. The method removes the need for each path being monitored to have a time reference (frame counter) of its own. Instead, each monitoring path has two accumulators whose active regions will overlap in time such that the total number of frames covered will be a power of 2. This approach allows one global frame counter to be used for all the paths in question, even if those paths have completely different accumulation periods. This method of performing BER tests allows devices to perform such operations on thousands of tributary paths (VT, TU), rather than only on the STS-n/STM-n paths that most current SONET/SDH devices support.

Claims

1. A method of determining an error level of a data channel, said method comprising:

receiving channel parity error data in the form of channel error events data that indicates bit error occurrences within a set of data carried on a channel data channel;

integrating said channel error events data on overlapping accumulation periods to form integrated channel error events data such that the total time in frames covered by two overlapping periods is a power of 2;

comparing said integrated channel error events data with a declaration threshold and a clearing threshold;

indicating an alarm when said integrated channel error events data exceeds said declaration threshold; and

removing an alarm when, upon finishing an accumulation period, said integrated channel error events data does not exceed said clearing threshold.

2. The method as claimed in claim 1 where all channels being monitored share a global frame counter without regard to programmed integration period length of any channel.

3. The method as claimed in claim 1 where each accumulation period, declaration threshold, and clearing threshold are programmable.

4. The method as claimed in claim 1 further including

recovering line or framing pulses from each data channel, and

deriving a clock time base from said pulses for the step of integrating said channel error events data.

5. A mechanism for determining an error level of a data channel, said mechanism comprising:

a path memory for storing all path information including bit error rate target (BER) monitoring threshold and alarm status;

a lookup table memory for programmably setting accumulation period and error threshold for each BER test;

a bit interleaved parity (BIP) error count memory for holding two BIP error accumulators for each path;

a path scheduler for selecting which path is currently being processed, and providing related addresses to said path memory and said BIP error count memory;

a global frame counter for counting frames by using an incoming frame reference; and

a monitor logic for performing comparison between accumulated errors and error threshold, and declaring and clearing alarms as appropriate.

6. The mechanism as claimed in claim 5 wherein said mechanism is embodied in hardware.

7. The mechanism as claimed in claim 5 wherein said mechanism is embodied in executable program instructions stored on a computer readable medium.

8. A method of determining an error level of a data channel, said method comprising:

reading path information based upon a path schedule block;

determining path type, target bit error rate, and whether to retrieve settings for alarm declaration or for alarm clearing;

based upon information of said determining step, obtaining appropriate settings for bit interleaved parity (BIP) threshold and integration period from a setting memory;

based upon said integration period and global frame count, determining whether a first accumulator is active, a second accumulator is active, or whether both are active;

retrieving BIP count memory for the appropriate path and accumulator depending on accumulator activity;

adding an incoming error count to accumulations as appropriate;

asserting or removing alarms as appropriate;

clearing error counts as appropriate;

writing a new error count to the BIP count memory; and

writing any change in alarm status to path memory.