Method and apparatus for controlling evaluation of protected intellectual property in hardware

• US 7,234,159 B1
• Filed: 01/07/2003
• Issued: 06/19/2007
• Est. Priority Date: 01/07/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Fox, Jeffrey R., Bryner, Roger, Lytle, Craig, Kadet, Brad
• Primary Examiner(s): Smithers; Matthew
• Application Number:
  US10/339,170
• Time in Patent Office: 1,624 Days
• Field of Search: 726/9, 710/124, 710/117, 714/55
• US Class Current: 726/9
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, systems, apparatus, methods and computer program products control use of hardware and software and IP implemented as user logic in a programmed device. The programmed device includes programmed logic that has designed logic and control logic. The designed logic includes user logic and protected logic such as IP cores, the use of which is to be controlled. The control logic includes a signal generator external to the designed logic. This signal generator contains clock means and a timeout circuit. A controller is connected to the programmed device by a tether. The controller periodically sends a keep alive signal via the tether to the signal generator. These keep alive signals may be single bit or multi-bit tokens which are processed in the programmed device by the signal generator. The signal generator disables the programmed device when the signal generator reaches a programmed time limit before receiving a keep alive signal from the controller. Disabling the programmed device can be accomplished by disabling either the user logic or the protected logic or both.

Claims

1. A system for controlling hardware and software, the system comprising:

a logic device having an input and further having programmed logic, the programmed logic comprising;

designed logic; and

control logic including a signal generator external to the designed logic and connected to the device input and the designed logic;

a token generator having an output; and

a tether connecting the device input to the token generator output;

wherein the token generator is configured to periodically send a token via the tether to the signal generator; and

further wherein the signal generator is configured to disable the logic device, the programmed logic or the designed logic in the absence of an authorizing token.

2. The system of claim 1 wherein the designed logic comprises user logic and protected logic.

3. The system of claim 1 wherein disabling the logic device comprises disabling the programmed logic.

4. The system of claim 3 wherein disabling the programmed logic causes the user logic or protected logic to be disabled.

5. The system of claim 1 wherein the control logic is generated by a controller external to the logic device.

6. The system of claim 1 wherein the token is a single bit token.

7. The system of claim 1 wherein the token is a multi-bit token.

8. The system of claim 1 wherein the device input is a JTAG port, a multi-purpose I/O, a general purpose I/O or a dedicated configuration input.

9. The system of claim 1 wherein the token generator is part of a computer system running a control program that issues the tokens.

10. The system of claim 1 wherein the logic device is a programmed PLD.

11. The system of claim 1 wherein the tether is a wireless link or a computer download cable.

12. The system of claim 1 wherein the programmed logic includes a disabling signal access that is a top level input of the programmed logic or a top level output of the programmed logic.

13. The system of claim 1 wherein the signal generator comprises:

clock means;

a token input; and

a timeout circuit connected to the clock means and to the token input;

wherein the timeout circuit comprises a counter that counts from an initial count value to a time limit unless the counter is reset prior to reaching the time limit; and

further wherein the counter is reset to the initial count value whenever a token is received by the token input before the counter reaches the time limit.

14. The system of claim 13 wherein the clock means comprises a ring oscillator and further wherein the counter comprises a linear feedback shift register connected to the ring oscillator.

15. The system of claim 13 wherein the signal generator further comprises:

a validation circuit connected to the token input and the timeout circuit, wherein the validation circuit is configured to check the validity of any token received at the token input and further configured to reset the timeout circuit whenever a valid token is received by the validation cut.

16. The system of claim 15 wherein the validation circuit comprises a rolling code token-passing validation configuration having a linear feedback shift register with a programmable polynomial seed.

17. The system of claim 1 wherein an authorizing token is a token received prior to achieving an elapsed time, wherein the elapsed time is a terminal count value and further wherein the signal generator is further configured to:

count from an initial count value to a terminal count value;

reset the count to the initial count value after a token is received at the device input if the terminal count value has not yet been reached; and

generate a disabling signal and send the disabling signal to disable the programmed logic when the signal generator reaches the terminal count.

18. A system for protecting software cores, comprising:

a logic device including user logic, protected logic and control logic, wherein the control logic is separate from the protected logic and is coupled to an input of the logic device and contains a signal generator;

the input of the logic device receives keep alive signals from an external source that are received by the control logic, such that the signal generator outputs a disable signal when a keep alive signal is not received within a preset time frame.

19. The system of claim 18 wherein the user logic is defined at least in part by a user and the protected logic is provided by a party other than the user.

20. The system of claim 19, wherein the core logic is provided to the user for evaluation purposes.

21. The system of claim 18 wherein the keep alive signals are sent by a controller through a tether to the logic device.

22. The system of claim 21 wherein the tether is a cable or wireless link.

23. The system of claim 18 wherein the keep alive signal is a single bit or multi-bit token.

24. A system for controlling hardware and software, the system comprising:

a programmed logic device having an input and further having programmed logic, the programmed logic comprising;

designed logic; and

control logic including a signal generator external to the designed logic and connected to the device input and the designed logic;

wherein the signal generator is configured to disable the programmed device after the signal generator reaches a preset condition.

25. The system of claim 24 wherein the signal generator comprises a timeout circuit having a counter, the counter starts counting when the programmed device is initially operated, and the signal generator disables the programmed logic after the time limit is reached.

26. The system of claim 24 wherein the design logic includes user logic and protected logic and the control logic can disable more than one instantiation of protected logic.

27. A method of controlling hardware and software, the method comprising:

programming a device to create a programmed device having programmed logic, the programmed logic comprising;

designed logic; and

control logic including a signal generator external to the designed logic and connected to the designed logic and to an input of the device;

periodically sending a keep alive signal from a controller to the device input via a tether;

and

disabling the programmed device when the signal generator reaches a programmed time limit before receiving a keep alive signal from the controller.

28. The method of claim 27 wherein the designed logic comprises user logic and protected logic.

29. The method of claim 27 wherein disabling the programmed device comprises disabling the programmed logic.

30. The method of claim 29 wherein disabling the programmed logic comprises disabling the user logic or the protected logic.

31. The system of claim 27 wherein the control logic is generated by the controller.

32. The method of claim 27 wherein each keep alive signal is a token.

33. The method of claim 32 wherein the token is a single bit token.

34. The method of claim 32 wherein the token is a multi-bit token.

35. The method of claim 27 wherein the device input is a JTAG port.

36. The method of claim 27 wherein the controller is a computer system running a control program that issues the keep alive signals.

37. The method of claim 27 wherein the programmed device is a programmed PLD.

38. The method of claim 27 wherein the programmed device is an ASIC emulator or an ASSP emulator.

39. The method of claim 27 wherein the programmed device is a logic device having optional or special features.

40. The method of claim 27 wherein the tether is a wireless link or a computer download cable.

41. The method of claim 27 wherein the programmed logic includes a disabling signal access that is a top level input of the programmed logic or a top level output of the programmed logic.

42. The method of claim 27 wherein the signal generator comprises:

clock means;

a keep alive signal input; and

a timeout circuit connected to the clock means and to the keep alive signal input;

wherein the timeout circuit comprises a counter that counts from an initial count value to the time limit unless the counter is reset prior to reaching the programmed time limit; and

further wherein the counter is reset to the initial count value whenever a keep alive signal is received by the keep alive signal input before the counter reaches the programmed time limit.

43. The method of claim 42 wherein the clock means comprises a ring oscillator and further wherein the counter comprises a linear feedback shift register connected to the ring oscillator.

44. The method of claim 42 wherein the signal generator further comprises:

a validation circuit connected to the keep alive signal input and the timeout circuit, wherein the validation circuit is configured to check the validity of any keep alive signal received at the keep alive signal input and further configured to reset the timeout circuit whenever a valid keep alive signal is received by the validation circuit.

45. The method of claim 44 wherein the validation circuit comprises a rolling code token-passing validation configuration having a linear feedback shift register with a programmable polynomial seed.

46. The method of claim 27 wherein the programmed time limit is a calendar date.

47. The method of claim 27 wherein the programmed time limit is an elapsed time.

48. The method of claim 47 wherein the elapsed time is a terminal count value and further wherein the signal generator is further configured to:

count from an initial count value to a terminal count value;

reset the count to the initial count value after a keep alive signal is received at the device input if the terminal count value has not yet been reached; and

generate a disabling signal and send the disabling signal to disable the programmed device when the signal generator reaches the terminal count.

49. An apparatus for controlling hardware and software, the system comprising:

a logic device having input means and further having programmed logic means, the programmed logic means comprising;

designed logic means; and

control logic means including signal generating means external to the designed logic means and connected to the device input means and the designed logic means;

control means having output means; and

tethering means connecting the input means to the output means;

wherein the control means is configured to periodically send a keep alive signal via the tethering means to the signal generating means; and

further wherein the signal generating means is configured to disable the logic device when the signal generating means reaches a programmed time limit before receiving a keep alive signal from the control means.

50. A computer readable storage medium having computer readable code stored therein, the computer readable code comprising:

a computer usable medium having computer readable code embodied therein, the computer readable code comprising;

computer code for programming a device to create a programmed device, wherein the programmed device comprises;

an input;

and programmed logic, wherein the programmed logic comprises;

designed logic; and

control logic including a signal generator external to the designed logic and connected to the device input and the designed logic;

computer code for periodically sending a keep alive signal from a controller to the device input via a tether; and

computer code for disabling the programmed device when the signal generator reaches a programmed time limit before receiving a keep alive signal from the controller.