Thin film transistor and pixel structure thereof

• US 7,235,813 B2
• Filed: 06/13/2005
• Issued: 06/26/2007
• Est. Priority Date: 08/04/2003
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Lai, Han-Chung
• Primary Examiner(s): Dickey; Thomas L.
• Application Number:
  US11/160,173
• Publication Number:
  US 20050218410A1
• Time in Patent Office: 743 Days
• Field of Search: 257/66, 257/72, 257/E29.137, 349/43
• US Class Current: 257/66
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A thin film transistor and a pixel structure with the same are disclosed. The thin film transistor includes a gate electrode with at least one notch, a gate dielectric layer, a source region, a drain region, and a channel layer. The gate electrode is on a substrate. The gate dielectric layer is on the substrate and covers the gate electrode. The source region is on the gate dielectric layer, wherein it is over a region outside the notch of the gate electrode and overlaps a portion of the gate electrode. The drain region is on the gate dielectric layer, wherein it is over the notch of the gate electrode and overlaps the gate electrode at the edge of the notch. Further, the channel layer is on the gate dielectric layer and between the source and drain regions. Due to asymmetric design of the source and drain regions, the parasitic capacitance change can be substantially reduced when a misalignment of the upper and lower metal layers occurs.

Claims

1. A thin film transistor, comprising:

a scan line, formed on a substrate;

a gate electrode, formed on the substrate and electrically connected to the scan line, wherein the gate electrode has at least one notch;

a gate dielectric layer, formed over the substrate, covering the scan line and the gate electrode;

a drain region, formed over the notch of the gate electrode and the drain region overlapping a portion of the gate electrode at the edge of the notch and a portion of scan line;

a trident source region, formed on the gate dielectric layer, wherein the trident source region comprises;

two first projecting portions formed on the gate dielectric layer, wherein the two first projecting portions are over a region outside the notch of the gate electrode and the two first projecting portions overlap a portion of the gate electrode;

a second projecting portion, formed over the scan line between the two first projecting portions, wherein the second projecting portion is shorter than the two first projecting portions; and

a connection portion, connecting the second projecting portion and the two first projecting portions; and

a channel layer, formed between the gate electrode and the drain and trident source regions.

2. The thin film transistor of claim 1, further comprising an etch stop layer formed between the channel layer and the drain and trident regions.

3. The thin film transistor of claim 1, further comprising an ohmic-contact layer formed between the channel layer and the drain and trident source regions.

4. The thin film transistor of claim 1, wherein the connection portion of the trident source region extends over the scan line.

5. The thin film transistor of claim 1, wherein the shape of the notch of the gate electrode is a triangle, a quadrilateral or a non-regular shape.

6. The thin film transistor of claim 1, further comprising a data line formed on the gate dielectric layer, the data line electrically connected to the trident source region.