Redundancy circuits hardened against single event upsets

• US 7,236,001 B2
• Filed: 09/02/2005
• Issued: 06/26/2007
• Est. Priority Date: 09/02/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Fulkerson, David E.
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US11/219,369
• Publication Number:
  US 20070052442A1
• Time in Patent Office: 662 Days
• Field of Search: 326/9, 326/10, 326/12, 326/14
• US Class Current: 326/12
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/0075 by using two redundant chains

Abstract

A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives a first data input and second data input from redundant logic blocks or from logic blocks designed to provide complementary outputs. The decision block provides an output that is at a same logic level as the first data input if the two data inputs are at expected logic levels during normal operating conditions (i.e., no disturbances). The decision block provides an output that is at a same logic level as a previous output of the decision block if the two data inputs are not at expected logic levels during normal operating conditions.

Claims

1. A method for hardening circuits against single event upsets, comprising in combination:

providing a decision block that includes a storage element that stores data as long as a first input and a second input to the decision block remain constant;

providing an output from the decision block having a same logic level as the first input if the first input and the second input are at expected logic levels; and

providing a previous output of the decision block if the first input and the second input are not at the expected logic levels.

2. The method of claim 1, wherein the first input is expected to be at a same logic level as the second input.

3. The method of claim 1, wherein the first input is expected to be at an opposite logic level as the second input.

4. The method of claim 1, wherein the second input is a delayed version of the first input.

5. The method of claim 1, further comprising clocking the first input and the second input into the decision block.

6. The method of claim 1, further comprising providing a complementary output from the decision block.

7. The method of claim 1, wherein the storage element is a latch.

8. A system for hardening circuits against single effect upsets, comprising in combination:

a first logic input;

a second logic input designed to have a same logic level as the first logic input; and

a decision block connected to the first logic input and the second logic input, wherein the decision block includes a storage element that stores data as long as a first input and a second input to the decision block remain constant, wherein the decision block provides a logic output, wherein the logic output is the same as the first logic input if the first logic input and second logic input are at a same logic level, and wherein the logic output is a previous value of the logic output if the first logic input and the second logic input are at opposite logic levels.

9. The system of claim 8, wherein the decision block includes two inverters and four NAND gates, wherein the first logic input and the second logic input are connected to inputs of a first NAND gate and the two inverters, wherein outputs of the two inverters are connected to inputs of a second NAND gate, wherein an output of the first NAND gate is connected to an input of the third NAND gate and an output of the second NAND gate is connected to an input of the fourth NAND gate, wherein an output of the third NAND gate is connected to an input of the fourth NAND gate and an output of the fourth NAND gate is connected to an input of the third NAND gate, and wherein the output of the third NAND gate is the logic output.

10. The system of claim 9, wherein the third and fourth NAND gates are hardened against single event upset.

11. The system of claim 9, wherein the first and second NAND gates are connected to a clock input.

12. The system of claim 11, wherein the decision block further includes four NAND gates connected to form a slave latch.

13. The system of claim 8, wherein the decision block further provides a complementary logic output.

14. A system for hardening circuits against single event upsets, comprising in combination:

a first logic input;

a second logic input designed to have an opposite logic level as the first logic input; and

a decision block connected to the first logic input and the second logic input, wherein the decision block includes a storage element that stores data as long as a first input and a second input to the decision block remain constant, wherein the decision block provides a logic output, wherein the logic output is the same as the first logic input if the first logic input and second logic input are at opposite logic levels, and wherein the logic output is a previous value of the logic output if the first logic input and the second logic input are at a same logic level.

15. The system of claim 14, wherein the decision block includes two inverters and four NAND gates, wherein the first logic input is connected to an input of a first inverter and an input of a first NAND gate, wherein the second logic input is connected to an input of a second inverter and an input of a second NAND gate, wherein an output of the first inverter is connected to an input of the second NAND gate and an output of the second inverter is connected to an input of the first NAND gate, wherein an output of the first NAND gate is connected to an input of the third NAND gate and an output of the second NAND gate is connected to an input of the fourth NAND gate, wherein an output of the third NAND gate is connected to an input of the fourth NAND gate and an output of the fourth NAND gate is connected to an input of the third NAND gate, and wherein the output of the third NAND gate is the logic output.

16. The system of claim 15, wherein the third and fourth NAND gates are hardened against single event upset.

17. The system of claim 15, wherein the first and second NAND gates are connected to a clock input.

18. The system of claim 14, wherein the decision block includes four inverters, wherein the first logic input is connected to an input of a first inverter and the second logic input is connected to an input of a second inverter, wherein an output of the first inverter is connected to an input of a third inverter and an output of a fourth inverter, wherein an output of the second inverter is connected to an input of the fourth inverter and an output of the third inverter, and wherein the output of the third inverter is the logic output.

19. The system of claim 18, wherein the third and fourth inverters have a first size and the first and second inverters have a second size, wherein the first size is greater than the second size.

20. The system of claim 19, wherein a size difference between the first size and the second size prevents the logic output from changing to a different logic level if the first and second logic inputs are at the same logic level.

21. The system of claim 14, wherein the decision block further provides a complementary logic output.