High-speed differential logic buffer

• US 7,236,011 B2
• Filed: 09/20/2004
• Issued: 06/26/2007
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Tam, Kimo Y. F.
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US10/945,323
• Publication Number:
  US 20060061391A1
• Time in Patent Office: 1,009 Days
• Field of Search: 326/27, 326/83, 326/86, 326/115, 327/109, 327/110, 327/111, 330/253
• US Class Current: 326/83
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence

Abstract

A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.

Claims

1. A circuit for a high speed digital buffer, the circuit comprising:

an active load circuit connected to an output of the high speed digital buffer, the buffer including a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs, each differential output including a medium threshold voltage active device including an isolated back gate biased to a potential near a device supply voltage, the active devices being coupled so as to form a differential load circuit;

wherein the active load circuit loads the buffer output with an active transinductance stage having;

i. a complex output impedance, and

ii. current flow provided by a current source flowing through the buffer output.

2. A circuit according to claim 1, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

3. A circuit according to claim 1, wherein the digital buffer is a current mode logic circuit.

4. A circuit according to claim 1, hither comprising:

for each active device, a gate impedance setting resistance coupled between a device voltage source and a device control terminal.

5. A circuit according to claim 1, further comprising:

a trickle current arrangement coupling he differential outputs to each other to allow a trickle flow of current.

6. A circuit according to claim 1, further comprising:

for each differential output, a trickle current arrangement coupled to a device supply voltage to allow a trickle flow of current.

7. A circuit according to claim 1, further comprising:

for each differential output, a series damping resistance coupling the output to the associated active load circuit.

8. A circuit for a high speed digital buffer, the circuit comprising:

an active load circuit connected to an output of the high speed digital buffer, the buffer including a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs, each differential output including a low threshold voltage active device including an isolated back gate biased to a potential near a device supply voltage, the active devices being coupled so as to form differential load circuit;

wherein the active load circuit loads the buffer output with an active transinductance stage having;

i. a complex output impedance, and

ii. current flow provided by a current source flowing through the buffer output.

9. A circuit according to claim 8, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

10. A circuit according to claim 8, further comprising:

a trickle current arrangement coupling the differential outputs to each other to allow a trickle flow of current.

11. A circuit according to claim 8, further comprising:

for each differential output, a trickle current arrangement coupled to a device supply voltage to allow a trickle flow of current.

12. A circuit according to claim 8, further comprising:

for each differential output, a series damping resistance coupling the output to the associated active load circuit.

13. A circuit according to claim 8, wherein the digital buffer is a current mode logic circuit.

14. A circuit according to claim 8, further comprising:

for each active device, a gate impedance setting resistance coupled between a device voltage source and a device control terminal.

15. A circuit according to claim 8, further comprising:

a trickle current arrangement coupling the differential outputs to each other to allow a trickle flow of current.

16. A circuit according to claim 8, further comprising:

for each differential output, a trickle current arrangement coupled to it device supply voltage to allow a trickle flow of current.

17. A circuit according to claim 8, further comprising:

for each differential output, a series damping resistance coupling the output to the associated active load circuit.

18. A circuit for a high speed digital buffer, the circuit comprising:

an active load circuit connected to an output of the high speed digital buffer and loading the buffer output with an active transinductance stage having a complex output impedance, wherein current flow for the active transinductance stage is provided by a current source flowing through the buffer output; and

for each active load device, an auxiliary drain current resistance which provides a load current path for a preceding circuit stage.

19. A circuit according to claim 18, wherein the digital buffer is a current mode logic circuit.

20. A circuit according to claim 18, further comprising:

for each active device, a gate impedance setting resistance coupled between a device voltage source and a device control terminal.

21. A circuit according to claim 18, further comprising:

a trickle current arrangement coupling the differential outputs to each other to allow a trickle flow of current.

22. A circuit according to claim 18, further comprising:

for each differential output, a trickle current arrangement coupled to a device supply voltage to allow a trickle flow of current.

23. A circuit according to claim 18, further comprising:

for each differential output, a series damping resistance coupling the output to the associated active load circuit.

24. A method for loading a high speed digital buffer, the method comprising:

coupling an active load circuit to an output of the high speed digital buffer, the buffer including a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs, each differential output including a medium threshold voltage active device coupled so as to form a differential load circuit; and

isolating and biasing a back gate of each active device to a potential near a device supply voltage;

wherein the active load circuit loads the buffer output with an active transinductance stage having;

i. a complex output impedance, and

ii. current flow provided by a current source flowing through the buffer output.

25. A method according to claim 24, further comprising:

coupling a back gate supply diode to a device supply voltage to provide the potential for each back gate.

26. A method according to claim 24, wherein the digital buffer is a current mode logic circuit.

27. A method according to claim 24, further comprising:

for each active device, coupling a gate impedance setting resistance between a device voltage source and a device control terminal.

28. A method according to claim 24, further comprising:

coupling a trickle current resistance between the differential outputs and a device supply voltage to allow a trickle flow of current.

29. A method according to claim 24, further comprising:

for each differential input, coupling an input load resistance between the input and a device supply voltage.

30. A method for loading a high speed digital buffer, the method comprising:

coupling an active load circuit to an output of the high speed digital buffer, the buffer including a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs, each differential output including a low threshold voltage active device coupled so as to form a differential load circuit; and

isolating and biasing a back gale of each active device to a potential near a device supply voltage;

wherein the active load circuit loads the buffer output with an active transinductance stage having;

i. a complex output impedance, and

ii. current flow provided by a current source flowing through the buffer output.

31. A method according to claim 30, further comprising:

coupling a back gate supply diode to a device supply voltage to provide the potential for each back gate.

32. A method according to claim 30, further comprising:

coupling a trickle current resistance between the differential outputs and a device supply voltage to allow a trickle flow of current.

33. A method according to claim 30, further comprising:

for each differential input, coupling an input load resistance between the input and a device supply voltage.

34. A method according to claim 30, wherein the digital buffer is a current mode logic circuit.

35. A method according to claim 30, further comprising:

for each active device, coupling a gate impedance selling resistance between a device voltage source and a device control terminal.

36. A method according to claim 30, further comprising:

coupling a trickle current resistance between the differential outputs and a device supply voltage to allow a trickle flow of current.

37. A method according to claim 30, further comprising:

for each differential input, coupling an input load resistance between the input and a device supply voltage.

38. A method for loading a high speed digital buffer, the method comprising:

coupling an active load circuit to an output of the high speed digital buffer;

loading the buffer out put with an active transinductance stage having a complex output impedance, wherein current flow for the active transinductance stage is provided by a current source flowing through the buffer output; and

providing an auxiliary drain current resistance to present a load current path for a preceding circuit stage.

39. A method according to claim 38, wherein the digital buffer is a current mode logic circuit.

40. A method according to claim 38, further comprising:

for each active device, coupling a gate impedance setting resistance between a device voltage source and a device control terminal.

41. A method according to claim 38, further comprising:

coupling a trickle current resistance between the differential outputs and a device supply voltage to allow a trickle flow of current.

42. A method according to claim 38, further comprising:

for each differential input, coupling an input load resistance between the input and a device supply voltage.

43. A circuit for high speed digital data, the circuit comprising:

a first active load device having an input terminal coupled to an output of a first digital buffer, the first active load device loading the buffer output with an active transinductance stage having a complex output impedance, the first active load device further including an output terminal coupled to a device supply voltage; and

a second active load device having an input terminal coupled to an output of a second digital buffer, the second active load device loading the buffer output with an active transinductance stage having a complex output impedance, the second active load device further including a control terminal circuit which controls gain of the second active device;

wherein the second digital buffer includes an input which is coupled to the output of the first digital buffer; and

wherein the output terminal of the first active load device is coupled to the control terminal circuit of the second active load device.

44. A circuit according to claim 43, wherein the digital buffers are current mode logic circuits.

45. A circuit according to claim 43, wherein each digital buffer includes a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs.

46. A circuit according to claim 45, further comprising:

for each differential output of each active load device, an active device coupled so as to form a differential load circuit.

47. A circuit according to claim 46, further comprising:

for each active device, a gate impedance setting resistance coupled between a device voltage source and a device control terminal.

48. A circuit according to claim 43, wherein the active load devices are medium threshold voltage devices.

49. A circuit according to claim 48, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

50. A circuit according to claim 43, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

51. A circuit according to claim 43, wherein the active load devices arc low threshold voltage devices.

52. A circuit according to claim 51, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

53. A circuit according to claim 52, wherein a back gate supply diode coup ed to the device supply voltage provides the potential for each back gate.

54. A circuit according to claim 43, further comprising:

a trickle current arrangement for each buffer, coupling the differential outputs to each other to allow a trickle flow of current.

55. A circuit according to claim 43, further comprising:

for each differential output, a trickle current arrangement coupled to a device supply voltage to allow a trickle flow of current.

56. A circuit according to claim 43, further comprising:

for each differential output, a series damping resistance coupling the output to the associated active load device.

57. A circuit according to claim 43, further comprising:

for each active load device, an auxiliary drain current resistance which provides a load current path for a preceding circuit stage.

58. A circuit according to claim 43, wherein the digital buffers are clock signal buffers.

59. A circuit according to claim 43, wherein the digital buffers are data signal buffers.

60. A crosspoint switch containing an active load circuit, the crosspoint switch comprising:

a circuit for high speed digital data including;

a first active load device having an input terminal coupled to an output of a first digital buffer, the first active load device loading the buffer output with an active transinductance stage having a complex output impedance, the first active load device further including an output terminal coupled to a device supply voltage; and

a second active load device having an input terminal coupled to an output of a second digital buffer, the second active load device loading the buffer o output with an active transinductance stage having a complex output impedance, the second active load device further including a control terminal circuit which controls gain of the second active device;

wherein the second digital buffer includes an input which is coupled to the output of the first digital buffer; and

wherein the output terminal of the first active load device is coupled to the control terminal circuit of the second active load device.

61. A method for loading a high speed digital data circuit, the method comprising:

providing a first active load device including;

i. coupling an input terminal of the first active load device to an output of a first digital buffer so as to load the buffer output with an active transinductance stage having a complex output impedance, and

ii. coupling an output terminal of the first active load device to a device supply voltage; and

providing a second active load device including;

i. coupling an input terminal of the second active load device to an output of a second digital buffer so as to load the buffer output with an active transinductance stage having a complex output impedance, and

ii. providing a control terminal circuit which controls gain of the second active device;

coupling an input of the second digital buffer to the output of the first digital buffer; and

coupling the output terminal of the first active load device to the control terminal circuit of the second active load device.

62. A method according to claim 61, wherein the digital buffers are current mode logic circuits.

63. A method according to claim 61, wherein each digital buffer includes a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs.

64. A method according to claim 63, further comprising:

for each differential output of each active load device, coupling an active device so as to form a differential load circuit.

65. A method according to claim 64, further comprising:

for each active device, coupling a gate impedance setting resistance between a device voltage source and a device control terminal.

66. A method according to claim 64, wherein the active devices are medium threshold voltage devices.

67. A method according to claim 66, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

68. A method according to claim 67, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

69. A method according to claim 64, wherein the active devices are low threshold voltage devices.

70. A method according to claim 69, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

71. A method according to claim 70, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

72. A method according to claim 64, further comprising:

for each buffer, coupling the differential outputs to each other with a trickle current arrangement to allow a trickle flow of current.

73. A method according to claim 64, further comprising:

for each differential output of each buffer, coupling a trickle current arrangement between the output and a device supply voltage to allow a trickle flow of current.

74. A method according to claim 64, further comprising:

for each differential output of each buffer, coupling a series damping resistance to the associated active load device.

75. A method according to claim 61, further comprising:

for each active load device, providing a load current path for a preceding circuit stage with an auxiliary drain current resistance.

76. A method according to claim 61, wherein the digital buffers are clock signal buffers.

77. A method according to claim 61, wherein the digital buffers are data signal buffers.