System and method for providing a low power receiver design

• US 7,236,212 B2
• Filed: 01/19/2001
• Issued: 06/26/2007
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Vorenkamp, Pieter, Carr, Frank
• Primary Examiner(s): Kostak; Victor R.
• Application Number:
  US09/766,048
• Publication Number:
  US 20010008430A1
• Time in Patent Office: 2,349 Days
• Field of Search: 348/725, 348/654, 348/731, 725/151, 455/130, 455/41, 455/73, 455/318, 455/179.1, 455/302, 455/188.1, 455/189.1, 455/190.1, 455/191.1, 455/202, 455/205, 455207-209
• US Class Current: 348/726
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. A receiver, comprising:

a substrate;

a first mixer that performs up-conversion and is disposed on the substrate;

a differential filter coupled to an output of the first mixer;

a second mixer that performs down-conversion and provides image rejection, disposed on the substrate and coupled to an output of the differential filter, wherein the second mixer. is a differential I/Q mixer;

a first polyphase circuit disposed on the substrate that provides I and Q local oscillator signals for mixing in the second mixer; and

a second polyphase circuit disposed on the substrate that combines I and Q output signals of the second mixer to complete the image rejection;

wherein the differential filter is external to the substrate and has a passband that is determined to pass an up-converted output of the first mixer.

2. The receiver of claim 1, wherein the differential filter is a surface acoustic wave (SAW) filter.

3. The receiver of claim 1, wherein the substrate is processed using CMOS.

4. The receiver of claim 1, wherein the first mixer and the second mixer are differential mixers.

5. The receiver of claim 1, wherein the differential filter removes at least one channel from a plurality of channels received from the output of the first mixer.

6. The receiver of claim 1, further comprising a first local oscillator disposed on said substrate and providing a first local oscillator signal to said first mixer.

7. The receiver of claim 6, wherein a frequency of said first local oscillator signal is varied to perform channel selection.

8. The receiver of claim 6, further comprising a second local oscillator disposed on said substrate and providing a second local oscillator signal to said first polyphase circuit.

9. The receiver of claim 8, wherein at least one of said first local oscillator signal and said second local oscillator signal are differential.

10. The receiver of claim 1, wherein said first mixer includes a differential input port, a differential output port, and a differential local oscillator port.

11. The receiver of claim 1, wherein said second mixer includes a differential input port, a differential output port, and a differential local oscillator port.

12. A method for processing a RF signal having a plurality of channels, comprising:

(1) mixing the RF signal with a first differential local oscillator signal to produce a first differential IF signal;

(2) removing at least one unwanted channel from the first differential IF signal using a differential filter having a passband that is higher in frequency than the RF signal to produce a second differential IF signal;

(3) adjusting the first local oscillator signal so that a selected channel in the plurality of channels is shifted into a passband of the differential filter;

(3a) generating a second differential local oscillator signal having I and Q components using a first polyphase circuit;

(4) mixing the second differential IF signal with a second differential local oscillator signal to produce a second differential IF signal, including combining I and Q differential if outputs in a second polyphase circuit to produce said second differential IF signal;

wherein steps (1), (3), (3a) and (4) are performed on a common substrate, and wherein step (2) is performed external to the common substrate.

13. The method of claim 12, wherein the plurality of channels are television channels.

14. The method of claim 12, further comprising the step of:

(5) removing at least one unwanted channel from the second differential IF signal.

15. The method of claim 12, further comprising the step of:

(5) performing automatic gain control on the second IF signal on the common substrate.

16. The method of claim 12, wherein step (4) includes the step of removing at least one unwanted image from the second differential IF signal.

17. A receiver for processing a plurality of channels, comprising:

a substrate;

a first differential mixer disposed on the substrate, and that performs up-conversion;

a differential filter coupled to an output of the first differential mixer and configured external to the substrate, wherein the differential filter has a passband that is determined to pass an up-converted output of the first differential mixer;

a second differential mixer, disposed on the substrate and coupled to an output of the differential filter, said seconddifferential mixer providing down-conversion and image rejection;

a first polyphase circuit disposed on the substrate that provides I and Q local oscillator signals to an input of said second differential mixer; and

a second polyphase circuit disposed on the substrate that combines I and Q output signals of the second differential mixer to complete the image rejection.

18. The receiver of claim 17, further comprising:

a first differential local oscillator disposed on said substrate and having an output coupled to a local oscillator port of said first differential mixer; and

a second differential local oscillator disposed on said substrate and having an output coupled a local oscillator port of said first polyphase circuit.

19. The receiver of claim 18, wherein a frequency of said first differential local oscillator is varied to perform channel selection in said first differential filter.