Method for erase-verifying a non-volatile memory capable of identifying over-erased and under-erased memory cells
First Claim
1. A method for erase verifying a single level, non-volatile memory cell, the method comprising:
- generating a first reference current as an input to a first comparator circuit;
generating a second reference current as an input to a second comparator circuit; and
comparing a bit line current from a column coupled to the non-volatile memory cell substantially simultaneously with the first reference current and the second reference current.
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Accused Products
Abstract
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
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Citations
16 Claims
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1. A method for erase verifying a single level, non-volatile memory cell, the method comprising:
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generating a first reference current as an input to a first comparator circuit; generating a second reference current as an input to a second comparator circuit; and comparing a bit line current from a column coupled to the non-volatile memory cell substantially simultaneously with the first reference current and the second reference current. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for erase verifying a single level, non-volatile memory cell, the method comprising:
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generating a first reference voltage as an input to a first comparator circuit; generating a second reference voltage as an input to a second comparator circuit; and comparing, substantially simultaneously, a bit line voltage from a colunm coupled to the non-volatile memory cell with the first reference voltage and the second reference voltage. - View Dependent Claims (8, 9)
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10. A method for erase verifying a single level, non-volatile memory cell, the method comprising:
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receiving a first reference current; converting the first reference current to a first reference voltage; receiving a second reference current; converting the second reference current to a second reference voltage; converting a bit line current, from the memory cell, to a bit line voltage; comparing, substantially simultaneously, the bit line voltage with the first reference voltage in a first comparator circuit and the second reference voltage in a second comparator circuit; and identifying if the memory cell is over-erased, under-erased or erased in response to the comparison. - View Dependent Claims (11, 12, 13)
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14. A method for erase verifying a single level, non-volatile memory cell, the method comprising:
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receiving a reference current; converting the reference current to a first reference voltage and a second reference voltage; converting a bit line current, from the memory cell, to a bit line voltage; comparing, substantially simultaneously, the bit line voltage with the first reference voltage in a first comparator circuit and the second reference voltage in a second comparator circuit; and identifying if the memory cell is over-erased, under-erased or erased in response to the comparison.
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15. A method for erase verifying a single level, non-volatile memory cell, the method comprising:
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generating a first reference current; generating a second reference current; simultaneously comparing a bit line current from a colun-m coupled to the non-volatile memory cell with the first reference current in a first comparator circuit and the second reference current in a second comparator circuit; identifying if the memory cell is over-erased, under-erased or erased; and correcting the memory cell if it is over-erased or under-erased.
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16. A method for erase verifying a single level, non-volatile memory cell comprising:
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generating a first reference voltage; generating a second reference voltage; simultaneously comparing a bit line voltage from a column coupled to the non-volatile memory cell with the first reference voltage in a first comparator circuit and the second reference voltage in a second comparator circuit; identifying if the memory cell is over-erased, under erased, or erased; and correcting the memory cell if it is over-erased or under-erased.
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Specification