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Erase verify for non-volatile memory using a bitline current-to-voltage converter

  • US 7,236,400 B2
  • Filed: 08/05/2005
  • Issued: 06/26/2007
  • Est. Priority Date: 08/30/2001
  • Status: Expired due to Term
First Claim
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1. A non-volatile memory comprising:

  • an array of non-volatile memory cells arranged in columns using bit lines;

    a verify circuit selectively coupled to the bit lines to determine if the memory cells have an erase level that is within an erase level window formed substantially simultaneously by first and second reference signals such that whether the memory cell is erased, over-erased, or under-erased is indicated by the erase level in relation to the erase level window; and

    a current-to-voltage converter coupled between a selected one of the bit lines and the verify circuit, the current-to-voltage converter comprising;

    a resistor; and

    an activation circuit having an input coupled to the resistor and an output coupled to the verify circuit.

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