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Forward link time delay for distributed antenna system

  • US 7,236,515 B1
  • Filed: 11/19/2001
  • Issued: 06/26/2007
  • Est. Priority Date: 11/19/2001
  • Status: Expired due to Fees
First Claim
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1. A rake receiver circuit for receiving multi-path signals, the rake receiver comprising:

  • a first rake finger circuit having a first variable delay element, where the first variable delay element is configured to receive a first delay control signal, the first delay control signal value being selected to align a first delay introduced by the first variable delay element with a first multi-path signal to produce a first correlated data signal;

    a second rake finger circuit having a second variable delay element, where the second variable delay element is configured to receive a second delay control signal, the second delay control signal value being selected to align a second delay introduced by the second variable delay element with a second multi-path signal to produce a second correlated data signal;

    a scan control circuit configured to receive the first and second correlated signals and, responsive thereto, generate the first and second delay control signals, where the scan control circuit is configured to generate the first delay control signal by;

    (i) varying the first delay control signal over a first predetermined range of values, (ii) measuring a signal power level of the first correlated data signal to determine a value of the first delay control signal corresponding to a highest measured signal power level of the first correlated data signal, and (iii) setting the first delay control signal to the value of the first delay control signal corresponding to the highest measured signal power level of the first correlated data signal for operation, and where the scan control circuit is further configured to generate the second delay control signal by;

    (i) varying the second delay control signal over a second predetermined range of values, (ii) measuring a signal power level of the second correlated data signal to determine a value of the second delay control signal corresponding to a highest measured signal power level of the second correlated data signal, and (iii) setting the second delay control signal to the value of the second delay control signal corresponding to the highest measured signal power level of the second correlated data signal for operation; and

    a summing circuit for summing the first and second correlated signals to produce a combined data signal.

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