Clock switching circuit for a hot plug

• US 7,237,053 B1
• Filed: 11/16/2000
• Issued: 06/26/2007
• Est. Priority Date: 01/28/2000
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Mitsuhashi, Masato, Shirai, Yoshiyuki
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US09/713,024
• Time in Patent Office: 2,413 Days
• Field of Search: 710/100, 710/300, 710/302, 710/52, 710/60, 710/104, 710/305, 710/316, 710/61, 713/400, 713/600, 713/501, 713/320, 326/93, 326/104, 326/62, 327/99, 327/100, 327/144, 327/145, 327/147, 327/158, 375/357, 375/376, 375/377
• US Class Current: 710/302
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004

Abstract

One aspect of the present invention is a clock switching circuit for switching between asynchronous first clock and second clock when connecting or disconnecting an interface cable having a hot-plug function. The clock switching circuit includes a first group of flip-flops for receiving an interface disconnection signal that corresponds to disconnection and connection of the interface cable in response to the first clock, and a second group of flip-flops for receiving the interface disconnection signal in response to the second clock.

Claims

1. A method for controlling a clock switching circuit, comprising:

receiving a basic clock signal from an outside;

receiving a PLL clock signal generated by a PLL circuit based on the basic clock signal, said PLL clock signal being faster than the basic clock;

receiving a switch signal for switching an output from the basic clock signal to the PLL clock signal;

inhibiting outputting the basic clock signal upon receiving a connection of an interface cable which transmits a high speed signal;

counting a predetermined number of the PLL clock signal after inhibiting outputting the basic clock signal; and

outputting the PLL clock signal after the number of the PLL clock signal, wherein the predetermined number is set according to the frequency difference between the basic clock frequency and the PLL clock frequency.

2. A clock signal switching circuit that switches an output from a basic clock to a fast clock comprising:

a PLL circuit that generates said fast clock whose frequency is more than twice as much as a frequency of the basic signal; and

an inhibiting circuit that selects said fast clock in response to a connecting of an interface cable which transmits a high speed signal and inhibits said fast clock in response to a disconnecting of the interface cable which transmits a high speed signal,

wherein said inhibiting circuit includes;

a first circuit for disappearing the basic clock as the output when the switching said output from said basic clock to said fast clock, and

a second circuit for inhibiting the fast clock until the basic clock disappears through the first circuit and for allowing the output of the fast clock when the switching said output from said basic clock to said fast clock.

3. A clock signal switching circuit that switches an output from a basic clock to a fast clock comprising:

a PLL circuit that generates said fast clock whose frequency is more than twice as much as a frequency of the basic signal; and

an inhibiting circuit that inhibits said fast clock in response to a connecting of an interface cable within a term which depends on a difference between said frequency of said basic clock and said frequency of said fast clock in the case of switching said output from said basic clock to said fast clock,

wherein said inhibiting circuit includes;

a first circuit for disappearing the basic clock as the output when the switching said output from said basic clock to said fast clock, and

a second circuit for inhibiting the fast clock until the basic clock disappears through the first circuit and for allowing the output of the fast clock when the switching said output from said basic clock to said fast clock.