Methods and apparatus for fabricating Chip-on-Board modules

• US 7,238,550 B2
• Filed: 02/20/2003
• Issued: 07/03/2007
• Est. Priority Date: 02/26/2002
• Status: Active Grant

• Current Assignee: Nichols-Ip PLLC
• Original Assignee: Tandon Group, Ltd
• Inventors: Peddle, Charles I.
• Primary Examiner(s): Zarneke; David A.
• Application Number:
  US10/371,800
• Publication Number:
  US 20030159278A1
• Time in Patent Office: 1,594 Days
• Field of Search: 438/118
• US Class Current: 438/118
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4899 Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/029 : having a programmable lay-out, i.e. adapted for choosing between a few possibilities
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 : Memory
• CPC Class Codes: H05K 2203/162 : Testing a finished product, e.g. heat cycle testing of solder joints patterns for electrical inspection or testing H05K1/0268
• CPC Class Codes: H05K 3/225 : Correcting or repairing of printed circuits H05K1/0292, H05K3/222, H05K3/288, H05K3/4685 take precedence
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

An improved method for fabricating Chip-on-Board memory modules using partially-defective memory chips or a combination of partially-defective and flawless memory parts, comprises mounting unpackaged (or a combination of packaged and unpackaged) memory parts to a printed circuit board using one or more selectively settable materials, testing and patching the memory parts, and providing a protective cover after a suitable combination of memory parts and patches produces a fully-functional memory module. Also, a new set of printed circuit boards designed to allow fabrication of memory modules using single-bit patching, any-bit patching, and DDR technology with unpackaged memory parts. In a preferred embodiment, the method and printed circuit boards mentioned above are combined to produce a number of low-cost memory modules using modern, available partially-defective and flawless memory parts.

Claims

1. A method of fabricating Chip-on-Board logic modules using selectively settable materials, said method comprising:

mounting unpackaged die using a first layer of selectively-settable material;

hardening a ring of said first layer of selectively-settable material around a periphery said unpackaged die;

covering said first layer of selectively-settable material with a second layer of selectively-settable material; and

capturing bonding wires connecting said unpackaged die to a printed circuit board in said second layer of selectively-settable material.

2. The method of claim 1, wherein part of said first layer of selectively-settable material extends above said unpackaged die.

3. The method of claim 1, wherein said capturing bonding wires comprises placing only a part of each of the bonding wires in said second layer of selectively-settable material, ten hardening said second layer of selectively settable material.

4. The method of claim 1, further comprising placing selectively settable material between said unpackaged die and said printed circuit board to provide a physical and thermal buffer.

5. The method of claim 4, wherein said selectively settable material between said unpackaged die and said printed circuit board is less cured than said first and second layers of selectively-settable material.

6. The method of claim 1, wherein said selectively settable materials comprise UV-settable materials.

33. The method of claim 1, further comprising forming said first layer of selectively-settable material in a ring around said unpackaged die.

34. The method of claim 1, wherein mounting said unpackaged die further comprises positioning said unpackaged die in said first layer of selectively-settable material in a desired position relative to said printed circuit board before said selectively-settable material is hardened and then performing said hardening of said first layer of selectively-settable material.

36. The method of claim 1, wherein said second layer of selectively-settable material is applied in a ring over said first layer of selectively-settable material.

37. The method of claim 1, wherein said second layer of selectively-settable material captures only a portion of each of said bonding wires.

38. The method of claim 1, further comprising placing a cover over said unpackaged die and attaching said cover a circuit board on which said unpackaged die is mounted, said cover not being in direct contact with said unpackaged die.

39. The method of claim 1, further comprising resting said bonding wires on said first layer of selectively-settable material prior to application of said second layer of selectively-settable material.

7. A method of fabricating a Chip-on-Board logic module using selectively settable materials, said method comprising:

mounting one or more electronic logic parts on a printed circuit board using said selectively settable materials;

selectively hardening areas of a selectively settable material;

attaching bonding wires between pads of said logic parts and pads of said printed circuit board;

applying selectively settable material to cover a portion of each of said bonding wires;

then, inspecting bonding wire connections;

readjusting bonding wires, if needed; and

hardening said selectively settable material that covers said bonding wires.

8. The method of claim 7, wherein said one or more selectively settable materials comprises UV-settable materials.

9. The method of claim 7, wherein said mounting one or more logic parts further comprises aligning the memory parts on said punted circuit board.

10. The method of claim 7, wherein said mounting one or logic parts using said selectively settable materials comprises applying a quantity of a selectively settable material between unpackaged logic pans and said printed circuit board.

11. The method of claim 7, wherein said mounting one or logic parts using said selectively settable materials further comprises applying a quantity of a selectively settable material around unpackaged logic parts.

12. The method of claim 10, wherein said selectively settable material between unpackaged logic pans and said printed circuit board is not hardened.

13. The method of claim 7, wherein said selectively hardening areas of said selectively settable material comprises hardening axing of selectively settable material around said unpackaged logic part.

14. The method of claim 7, wherein one selectively settable material is used.

15. The method of claim 7, wherein more than one selectively settable materials are used.

16. The method of claim 7, wherein a selectively settable material used between an unpackaged logic part and a printed circuit board is never hardened, while a selectively settable material used around said unpackaged logic part is hardened.

35. The method of claim 7, wherein said logic parts comprise memory parts.

17. A method of fabricating Chip-on-Board logic modules using selectively settable materials, said method comprising:

mounting unpackaged die on a circuit board using a first layer of selectively-settable material;

hardening a portion of said first layer of selectively-settable material such that said unpackaged die is secured to said circuit board, but some of said selectively-settable material between said unpackaged die and said circuit board is never fully hardened.

18. The method of claim 17, wherein part of said first layer of selectively-settable material extends above said unpackaged die.

19. The method of claim 17, further comprising:

applying a second layer of selectively-settable material over said first layer of selectively-settable material; and

hardening said second layer of selectively-settable material so as to capture bonding wires connecting said unpackaged die to a printed circuit board in said hardened second layer of selectively-settable material.

20. The method of claim 19, wherein said capturing bonding wires comprises placing only a part of each of the bonding wires in said second layer of selectively-settable material, then hardening said second layer of selectively settable material.

21. The method of claim 17, wherein said selectively-settable material between said unpackaged die and said printed circuit board provides a physical and thermal buffer.

22. The method of claim 17, wherein said selectively settable material between said unpackaged die and said printed circuit board is in a liquid form.

23. The method of claim 17, wherein said selectively settable material between said unpackaged die and said printed circuit board is less cured said first layer of selectively-settable material.

24. The method of claim 17, wherein said selectively settable material comprises a UV-curable material.

25. A Chip-on-Board logic module using selectively settable materials, said module comprising:

a circuit board;

an unpackaged die mounted on said circuit board using a first layer of selectively-settable material, wherein a portion of said first layer of selectively-settable material has been hardened such that said unpackaged die is secured to said circuit board, but some of said selectively-settable material between said unpackaged die and said circuit board is never fully hardened.

26. The module of claim 25, wherein part of said first layer of selectively-settable material extends above said unpackaged die.

27. The module of claim 25, further comprising:

a hardened second layer of selectively-settable material applied over said first layer of selectively-settable material; and

a plurality of bonding wires connecting said unpackaged die to said circuit board, wherein said bonding wires are at least partially captured in said hardened second layer of selectively-settable material.

28. The module of claim 25, wherein said selectively-settable material between said unpackaged die and said printed circuit board provides a physical and thermal buffer.

29. The module of claim 25, wherein said selectively settable material between said unpackaged die and said printed circuit board is in a liquid form.

30. The module of claim 25, wherein said selectively settable material between said unpackaged die and said printed circuit board is less cured said first layer of selectively-settable material.

31. The module of claim 25, wherein said selectively settable material comprises a UV-curable material.

32. The module of claim 25, wherein said unpackaged die has one or more faulty input/output lines which are compensated for by input/output lines of another unpackaged die mounted on said circuit board.