Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys

• US 7,238,551 B2
• Filed: 11/23/2004
• Issued: 07/03/2007
• Est. Priority Date: 11/23/2004
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Chen, Chang-Sheng, Wang, Peter, Owyang, King, Kasem, Mohammed, Mao, Sen, Kuo, Frank, Ou, Oscar, Jaunay, Serge Robert
• Primary Examiner(s): Menz; Douglas M.
• Application Number:
  US10/996,149
• Publication Number:
  US 20060110856A1
• Time in Patent Office: 952 Days
• Field of Search: 438/106, 438/121, 438/123
• US Class Current: 438/123
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73153 Bump and layer connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Claims

1. A method of fabricating a semiconductor package comprising:

providing a lower lead frame, said lower lead frame having at least a first contact;

forming a plurality of raised mesas in said first contact, said mesas having top surfaces and being separated by valleys;

dispensing a first plurality of solder paste drops only on said top surfaces of said mesas;

placing a semiconductor die on said first plurality of solder paste drops;

performing a first reflow of said first plurality of solder paste drops so as form a first solder layer between said die and said first contact, said first reflow causing the first solder layer to flow into said valleys thereby decreasing a separation distance between said die and said first contact;

dispensing a second plurality of solder paste drops on a top surface of said die;

placing an upper lead frame on said second plurality of solder paste drops, said upper lead frame comprising bent portions at opposite ends of said upper lead frame, each of said bent portions terminating in a foot, said bent portions extending downward around opposite edges of said die;

performing a second reflow of said plurality of solder paste drops and said first solder layer.

2. The method of claim 1 wherein said lower lead frame further comprises at least two outside contacts, said outside contacts being located on opposite sides of said first contact, said method comprising dispensing a third plurality of solder paste drops on each of in said outside contacts and bringing said feet into contact with said third plurality of solder drops.

3. The method of claim 1 wherein during said second reflow at least a portion of said first solder layer flows from said valleys.

4. The method of claim 1 wherein a vertical distance between said first contact and said die increases during said second reflow.

5. The method of claim 1 wherein forming said mesa comprises etching said first contact so as to form said valleys.

6. The method of claim 2 comprising:

forming a cavity in a top surface of each of said outside contacts;

dispensing said third plurality of solder paste drops in said cavities.

7. A method of fabricating a package comprising a MOSFET die, the MOSFET die having a source terminal and a gate terminal on a first surface of the die and a drain terminal on a second surface of the die, the method comprising:

providing a lower lead frame, said lower lead frame comprising a source contact, a gate contact and at least two drain contacts,

providing an upper lead frame, said upper lead frame being cup-shaped and having at least two bent portions on opposite sides of said upper lead frame, said bent portions terminating in feet;

forming a plurality of mesas in said source contact, said mesas having top surfaces and being separated by valleys;

forming at least one cavity in each of said drain contacts;

dispensing a plurality of solder paste drops on said source contact, said paste drops resting on said top surfaces of said mesas but not filling said valleys;

dispensing solder paste on said gate contact;

placing said MOSFET die on said solder paste drops, the source terminal of said die being in contact with said plurality of solder paste drops, the gate terminal of said die being in contact with said solder paste on said gate contact;

performing a first reflow of said solder paste drops and said solder paste on said gate contact so as form a first solder layer between said source terminal and said source contact and a second solder layer between said gate terminal and said gate contact, said first reflow causing the first solder layer to flow into said valleys thereby decreasing a separation distance between said die and said source and gate contacts;

dispensing solder paste into said at least one cavity in each of said drain contacts;

dispensing solder paste on said drain terminal of said die;

placing said upper lead frame on said solder paste on said drain terminal and said solder paste in said at least one cavity, the feet of said upper lead frame resting on said solder paste in said at least one cavity; and

performing a second reflow of said first solder layer and said solder paste on said drain terminal and in said at least one cavity, said second reflow forming a second solder layer between said upper lead frame and said die, said second reflow causing said die to lift from said source and gate contacts and causing at least a portion of said first solder layer to flow out of said valleys.

8. The method of claim 7 comprising forming longitudinal openings in said upper lead frame at the locations of said at least two bent portions.

9. The method of claim 7 comprising forming four bent portions in said upper lead frame.

10. The method of claim 7 wherein said mesas are formed by etching said lower lead frame.

11. The method of claim 7 wherein said mesas are formed by stamping said lower lead frame.

12. The method of claim 7 comprising forming a groove in a lower surface of said upper lead frame.

13. The method of claim 12 wherein said groove is X-shaped.

14. The method of claim 12 comprising forming a series of parallel grooves the lower surface of said upper lead frame.

15. The method of claim 7 comprising applying molding compound to said leadframes and die after said second reflow, said molding compound flowing into said valleys of said source contact.

16. The method of claim 7 where a thickness ratio between said second solder layer and said first solder layer after said second reflow is in the range of 1:

2 to 1;

10.

17. The method of claim 7 wherein a thickness of said first solder layer is greater than 2.0 mils and a thickness of said second solder layer is less than 1.2 mils.

18. The method of claim 17 wherein a thickness of said first solder layer is 3.5 mils and a thickness of said second solder layer is 0.8 mils.