Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same

• US 7,238,568 B2
• Filed: 05/25/2005
• Issued: 07/03/2007
• Est. Priority Date: 05/25/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne B.
• Primary Examiner(s): Lindsay, Jr.; Walter
• Assistant Examiner(s): DINH, THU HUONG T
• Application Number:
  US11/137,151
• Publication Number:
  US 20050215013A1
• Time in Patent Office: 769 Days
• Field of Search: 438/243, 257/397, 257/E27.093, 257/E21.422, 257/E21.546, 257/E21.572, 257/E21.549, 257/E21.551
• US Class Current: 438/243
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

Claims

1. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a mask layer on a surface of said semiconductor material;

forming a opening in said mask layer;

forming a trench in said semiconductor material by etching said semiconductor material through said opening;

forming an oxide lining on a bottom and sidewalls of said trench;

depositing a first polysilicon layer in said trench;

etching said first polysilicon layer such that a remaining portion of said first polysilicon layer remains over said oxide lining at the bottom of said trench;

removing said oxide lining except for a remaining portion of said oxide lining that is adjacent said remaining portion of said first polysilicon layer;

anisotropically etching a top surface of said remaining portion of said first polysilicon layer so as to depress said top surface to a level below a top surface of said remaining portion of said oxide lining;

heating said device so as to form a first oxide layer on said top surface of said first polysilicon layer and a second oxide layer on exposed portions of said sidewalls of said trench;

removing said first oxide layer while leaving a portion of said second oxide layer on the sidewalls of said trench; and

depositing a second polysilicon layer in said trench.

2. The process of claim 1 wherein said second polysilicon layer extends over said surface of said semiconductor material, said process comprising etching said second polysilicon layer such that a surface of said second polysilicon layer is substantially coplanar with said surface of said semiconductor material.

3. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a mask layer on a surface of said semiconductor material;

forming a opening in said mask layer;

forming a trench in said semiconductor material by etching said semiconductor material through said opening;

forming an oxide lining on a bottom and sidewalls of said trench;

depositing a photoresist layer in said trench;

washing said photoresist layer such that a remaining portion of said photoresist layer remains over said oxide lining at the bottom of said trench;

removing said oxide lining except for a remaining portion of said oxide lining that is adjacent said remaining portion of said photoresist layer, thereby leaving exposed portions of said sidewalls of said trench;

removing said remaining portion of said photoresist layer;

growing a gate oxide layer on said exposed portions of said sidewalls of said trench; and

depositing a polysilicon layer in said trench.