Semiconductor device and method of producing a semiconductor device

• US 7,238,974 B2
• Filed: 10/29/2004
• Issued: 07/03/2007
• Est. Priority Date: 10/29/2004
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Riedel, Stephan, Strassburg, Matthias
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US10/978,216
• Publication Number:
  US 20060091424A1
• Time in Patent Office: 977 Days
• Field of Search: 257/208, 257/209, 257/315
• US Class Current: 257/208
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises a memory cell (160) including a transistor body (150) having a top surface (111) and including a first doping area (10a) and a second doping area (10b) with a channel region (110) in between. The memory cell (160) further includes a gate electrode (3a) arranged above the channel region (110) and separated therefrom by a dielectric layer (2a). An oxide-nitride-oxide layer (66) has first portions (661) and second portions (662). The first portions (661) of the oxide-nitride-oxide layer (66) are arranged above at least parts of the first and second doping areas (10a, 10b) and are substantially parallel to the top surface (111) of the transistor body (150). The second portions (662) of the oxide-nitride-oxide layer (66) are adjacent to the gate electrode (3a) and extend in a direction not substantially parallel to the top surface (111) of the transistor body (150).

Claims

1. A semiconductor device comprising:

a transistor body having a top surface and having a first doping area and a second doping area, and a channel region between the first doping area and the second doping area;

a gate dielectric located over the top surface of the transistor body;

a gate electrode disposed above the channel region and disposed on the gate dielectric such that the gate dielectric is located between the gate electrode and the top surface of the transistor body;

a first portion of an oxide-nitride-oxide layer disposed above the first and second doping areas and the first portions of the oxide-nitride-oxide layer having a first surface substantially parallel to the top surface of the transistor body and said first portion further including a second surface;

a second portion of the oxide-nitride-oxide layer extending in a direction not substantially parallel to the top surface of the transistor body and said second portion having a first surface located adjacent to the gate electrode and said second portion also having a second surface; and

a nitride spacer for insulating said gate electrode arranged vertical with respect to the top surface of the transistor body and located on the second surface of said first and second portions.

2. The semiconductor device according to claim 1, wherein the second portions of the oxide-nitride-oxide layer extend substantially orthogonal with respect to the first portions of the oxide-nitride-oxide layer.

3. The semiconductor device according to claim 1, wherein the first surfaces of the first portions of the oxide-nitride-oxide layer are in contact with the top surface of the transistor body, and the first surfaces of the second portions of the oxide-nitride-oxide layer are in contact with sidewalls of the gate electrode.

4. The semiconductor device according to claim 1, wherein the gate electrode comprises polysilicon.

5. The semiconductor device according to claim 1, wherein the gate dielectric layer comprises one of silicon dioxide or silicon oxide.

6. The semiconductor device according to claim 1, wherein the channel region is doped with a dopant comprising either boron and/or indium, and wherein the first and second doping areas are doped with arsenic.

7. The semiconductor device according to claim 1, further comprising a plurality of memory cells, the memory cells being arranged in a matrix having columns and rows, the rows aligned to a first direction, the columns aligned to a second direction, the second direction orthogonal with respect to the first direction.

8. The semiconductor device according to claim 7, wherein a subset of the first and second doping areas of the plurality of the memory cells arranged in the same one of rows is aligned with a line parallel to the first direction.

9. The semiconductor device according to claim 7, wherein the second portions of the oxide-nitride-oxide layer extend substantially orthogonal with respect to the first portions of the oxide-nitride-oxide layer.

10. The semiconductor device according to claim 7, wherein the first surfaces of the first portions of the oxide-nitride-oxide layer are in contact with the top surface of the transistor body, and the first surfaces of the second portions of the oxide-nitride-oxide layer are in contact with sidewalls of the gate electrode.

11. The semiconductor device according to claim 7, wherein the gate electrode comprises polysilicon.

12. The semiconductor device according to claim 7, wherein the dielectric layer comprises one of silicon dioxide or silicon oxide.

13. The semiconductor device according to claim 7, wherein the channel region is doped with a dopant, said dopant comprising one of boron and/or indium, and wherein the first and second doping areas are doped with arsenic.

14. The semiconductor device according to claim 7, further comprising dopants having anti-punch characteristics disposed between adjacent rows of gate electrodes and extending parallel to the first direction, the dopants being located beneath the top surface of the transistor body.

15. The semiconductor device according to claim 7, further comprising a bitline disposed parallel to the second direction, the bitline electrically coupling at least two adjacent doping areas located parallel to the second direction.

16. The semiconductor device according to claim 15, further comprising an oxide line disposed on the bitline, the oxide line disposed between the first portions of the oxide-nitride-oxide layer.

17. The semiconductor device according to claim 7, further comprising a wordline, the wordline electrically connected to at least two of a multitude of gate electrodes arranged in a same one of the rows.

18. The semiconductor device according to claim 17, wherein the wordline comprises one or more materials selected from the group consisting of polysilicon, metal and metal suicide.

19. The semiconductor device according to claim 18 wherein the wordline comprises tungsten silicide.

20. The semiconductor device of claim 1:

wherein the transistor body is formed in a substrate having a top surface;

wherein the gate electrode is one of a multitude of gate electrodes disposed on the top surface of the substrate, the gate electrodes disposed in an array having rows located parallel to a first direction and columns located parallel to a second direction, which is orthogonal with respect to the first direction;

wherein the gate dielectric is one of a multitude of gate dielectrics;

wherein the first doping area and the second doping area are part of a first bitline and a second bitline, respectively, the first and second bitlines disposed along the second direction on either side of a column of the gate electrodes, the bitlines buried beneath the top surface of the substrate; and

wherein the a channel region is disposed in the substrate between the bitlines and beneath the gate electrode.

21. The semiconductor device according to claim 20, wherein the second portions of the oxide-nitride-oxide layer extend substantially orthogonal with respect to the first portions of the oxide-nitride-oxide layer.

22. The semiconductor device according to claim 20, wherein the first surfaces of the first portions of the oxide-nitride-oxide layer are in contact with the top surface of the substrate, and the first surfaces of the second portions of the oxide-nitride-oxide layer are in contact with sidewalls of the gate electrode.

23. The semiconductor device according to claim 20, wherein the gate electrodes comprise polysilicon.

24. The semiconductor device according to claim 20, wherein the gate dielectric comprises one of silicon dioxide or silicon oxide.

25. The semiconductor device according to claim 20, wherein the channel region is doped with boron and/or indium;

and wherein the first and second doping areas are doped with arsenic.

26. The semiconductor device according to claim 20, further comprising dopants having anti-punch characteristics disposed between adjacent rows of gate electrodes and extending parallel to the first direction, the dopants located beneath the top surface of the substrate.

27. The semiconductor device according to claim 20, further comprising at least two oxide lines, each disposed on one of the bitlines, each oxide line disposed between the first portions of the oxide-nitride-oxide layer.

28. The semiconductor device according to claim 20, further comprising a wordline that is electrically connected to at least two of the multitude of gate electrodes arranged in a same one of the rows.

29. The semiconductor device according to claim 28, wherein the wordline comprises one or more materials selected from the group consisting of polysilicon, metal and metal silicide.

30. The semiconductor device of claim 1 further comprising an oxide line separating first portions of said oxide-nitride-oxide layer.

31. The semiconductor device of claim 30 further comprising a bit line below said oxide line.