Capacitor-built-in type printed wiring substrate, printed wiring substrate, and capacitor

• US 7,239,014 B2
• Filed: 07/07/2005
• Issued: 07/03/2007
• Est. Priority Date: 03/30/1999
• Status: Expired due to Term

• Current Assignee: NGK Spark PLUG Company Limited (Niterra Co., Ltd.)
• Original Assignee: NGK Spark PLUG Company Limited (Niterra Co., Ltd.)
• Inventors: Kodera, Eiji, Ogawa, Kouki
• Primary Examiner(s): Ha; Nathan W.
• Application Number:
  US11/175,154
• Publication Number:
  US 20050258548A1
• Time in Patent Office: 726 Days
• Field of Search: 257700-777, 257/778, 257734-738
• US Class Current: 257/700
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/236 leading through the housing, i.e. lead-through
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/16268 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H05K 1/0231 : Capacitors or dielectric substances
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2203/047 : Soldering with different solders, e.g. two different solders on two sides of the PCB
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A capacitor-built-in-type printed wiring substrate which can reliably eliminate noise and attain extremely low resistance and low inductance in connections between an IC chip and the capacitor, and a printed wiring substrate and capacitor for use in the same. A capacitor-built-in-type printed wiring substrate 100 on which an IC chip is mounted includes a capacitor-built-in-type printed wiring substrate 110 and an IC chip 101 mounted on the capacitor-built-in-type printed wiring substrate 110. A printed wiring substrate 120 includes a number of connection-to-IC substrate bumps 152 and a closed-bottomed capacitor accommodation cavity 121 formed therein. A capacitor 130 is disposed in the cavity 121 and includes a pair of electrode groups 133E and 133F and a number of connection-to-IC capacitor bumps 131 connected to either one of the paired electrode groups 133E and 133F. The connection-to-IC capacitor bumps 131 are flip-chip-bonded to corresponding connection-to-capacitor bumps 103 on the IC chip 101. The connection-to-IC substrate bumps 152 are flip-chip-bonded to corresponding connection-to-substrate bumps 104 on the IC chip 101.

Claims

1. A capacitor-built-in-type printed wiring substrate for mounting an IC chip or IC-chip-carrying printed wiring substrate, comprising:

a wiring substrate (520), and

a capacitor (530) having on respective opposite sides thereof first and second substantially parallel capacitor main surfaces (530A, 530B), said capacitor comprising;

a pair of electrodes (533E, 533F) or of electrode groups, the electrodes being disposed in a plurality of electrode layers (533) formed between dielectric layers (532);

a plurality of first capacitor terminals (534,531) arranged on the first capacitor main surface and capable of being respectively flip-chip-bonded or bonded in a connection-face-to-connection-face manner to a plurality of connection-to-capacitor terminals (503) of the IC chip or IC-chip-carrying printed wiring substrate;

via conductors (535E, 535F) extending through the dielectric layers and electrically connecting each said first capacitor terminal to a respective one of said pair of electrodes or of electrode groups, each one of said pair of electrodes or of electrode groups being electrically connected to at least one of the plurality of first capacitor terminals; and

a plurality of second capacitor terminals (536A, 536B, 536C) arranged on the second capacitor main surface and electrically connected to a wiring layer (575) of the wiring substrate,

wherein the printed wiring substrate comprises a plurality of substrate terminals (551, 552) capable of being respectively flip-chip-bonded or bonded in a connection-face-to-connection-face manner to a plurality of connection-to-substrate terminals (504) of the IC chip or IC-chip-carrying printed wiring substrate;

characterized in that the capacitor is fixed in a capacitor accommodation cavity formed in the printed wiring substrate by means of insulating resin (523A), and in that the plurality of second capacitor terminals (536) are disposed at intervals greater than those of the plurality of first capacitor terminals (534).

2. The capacitor-built-in-type printed wiring substrate according to claim 1, wherein the printed wiring substrate comprises:

a first substrate main-surface (520A), on which the plurality of substrate terminals (551, 552) are formed, the first capacitor terminals and the substrate terminals being coplanar, and

a cavity periphery region located around the capacitor accommodation cavity, said plurality of substrate terminals being formed in the cavity periphery region.

3. The capacitor-built-in-type printed wiring substrate according to claim 1, wherein the capacitor accommodation cavity comprises a capacitor position restriction portion (747T) which abuts the capacitor (530) disposed therein so as to restrict a position of the capacitor in a depth direction thereof.

4. The capacitor-built-in-type printed wiring substrate according to claim 1, wherein:

the printed wiring substrate is plate-shaped and has a first substrate main-surface (520A) and a second substrate main-surface (520B), the capacitor accommodation cavity being closed-bottomed and sunk below the first substrate main-surface toward the second substrate main-surface, said printed wiring substrate including;

a plurality of second-surface substrate terminals (562, 564) formed on the second substrate main-surface; and

a plurality of connection lines (571) extending from some of the plurality of second-surface substrate terminals (564) to a bottom surface (521S) of the closet-bottomed capacitor accommodation cavity;

each of said plurality of second-surface capacitor terminals (536) is electrically connected to a respective one of said pair of electrodes or of electrode groups, each one of said pair of electrodes or of electrode groups being electrically connected to at least one of the plurality of second-surface capacitor terminals;

the plurality of substrate terminals (552) are formed on the first substrate main-surface (520A); and

the plurality of second-surface capacitor terminals (536) are connected to the corresponding connection lines (571) which extend to the bottom surface of the closed-bottomed capacitor accommodation cavity.

5. The capacitor-built-in-type printed wiring substrate according to claim 1, wherein:

the printed wiring substrate is plate-shaped and has a first substrate main-surface (720A) and a second substrate main-surface (720B), the capacitor accommodation cavity being in the form of a through-hole which extends through the printed wiring substrate from the first substrate main-surface to the second substrate main-surface, said printed wiring substrate including;

a plurality of second-surface substrate terminals (744B) formed on the second substrate main-surface;

each of said a plurality of second-surface capacitor terminals (736) is electrically connected to a respective one of said pair of electrodes or of electrode groups, each one of said pair of electrodes or of electrode groups being electrically connected to at least one of the plurality of second-surface capacitor terminals; and

the plurality of substrate terminals (743P) are formed on the first substrate main-surface (720A).

6. The capacitor-built-in-type printed wiring substrate according to claim 1 on which an IC-chip-carrying printed wiring substrate is mounted, wherein the IC-chip-carrying printed wiring substrate is a CSP on which an IC chip is mounted.

7. The capacitor-built-in-type printed wiring substrate according to claim 1, wherein the first main surface of the capacitor is covered by an insulating resin (550).

8. A capacitor to be attached to a printed wiring substrate so as to form a capacitor-built-in type printed wiring substrate, and to be connected, when so attached, to an IC chip or IC-chip-carrying printed wiring substrate, the capacitor comprising:

a pair of electrodes (533E, 533F) or of electrode groups, the electrodes being disposed in a plurality of electrode layers (533) formed between dielectric layers (532);

a plurality of first capacitor terminals (534,531) capable of being respectively flip-chip-bonded or bonded in a connection-face-to-connection-face manner to a plurality of connection-to-capacitor terminals (503) of the IC chip or IC-chip-carrying printed wiring substrate, each of said first capacitor terminals being electrically connected to a respective one of said pair of electrodes or of electrode groups, each one of said pair of electrodes or of electrode groups being electrically connected to at least one of the plurality of first capacitor terminals;

a plurality of second capacitor terminals (536) for electrical connection to the printed wiring substrate; and

via conductors (535E, 535F) extending through the dielectric layers and electrically connecting the first and second capacitor terminals,

characterized in that the plurality of second capacitor terminals are disposed at intervals greater than those of the plurality of first capacitor terminals.