Primary-side feedback switching power supply

• US 7,239,532 B1
• Filed: 12/27/2006
• Issued: 07/03/2007
• Est. Priority Date: 12/27/2006
• Status: Expired due to Fees

• Current Assignee: Niko Semiconductor Co., Ltd
• Original Assignee: Niko Semiconductor Co., Ltd
• Inventors: Hsu, Da-Jing, Yang, Hui-Qiang
• Primary Examiner(s): Vu; Bao Q.
• Application Number:
  US11/645,772
• Time in Patent Office: 188 Days
• Field of Search: 363/21.12, 363/21.16, 363/21.17, 363/21.18
• US Class Current: 363/21.12
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop

Abstract

The present invention discloses a primary-side feedback switching power supply that uses a sample-and-hold circuit to obtain a corner voltage of a harmonic wave voltage while the primary-side auxiliary winding is operating at a discontinuous mode as a feedback control, and provides both voltage regulation and current limit functions. A stable voltage output is provided within the nominal input voltage and nominal output load, such that when the output reaches a current limit, the output voltage drops but the output current is controlled to remain unchanged, so as to provide an over-current protection.

Claims

1. A primary-side feedback switching power supply, comprising:

a flyback transformer, having a primary winding, an auxiliary winding and a secondary winding, and said primary winding being connected to a power source;

a power transistor, connected to said primary winding;

a primary-side feedback PWM controller, comprising;

a sample-and-hold control circuit, connected to said auxiliary winding;

an error amplifier, connected to said sample-and-hold circuit;

a voltage divider, connected to said sample-and-hold circuit;

a multiplier, connected to said voltage divider;

a first comparator, connected to said error amplifier and said power transistor;

a second comparator, connected to said first comparator and said multiplier;

a power limit compensation circuit, connected to said multiplier;

a switch, connected to said power source and said power limit compensation circuit;

an output driver, connected to said power transistor;

a flip-flop, connected to said output driver;

an oscillator, connected to said flip-flop;

a leading edge blanking circuit, connected to said flip-flop;

an OR gate, connected to said first comparator, said second comparator and said leading edge blanking circuit;

such that if the supply source voltage reaches a turning on threshold level to start said primary-side feedback PWM controller, a low voltage latching circuit will control said switch to be conducted electrically, and said power limit compensation circuit will produce a power limit compensation voltage to be sent to said multiplier input terminal;

said oscillator will produce an electrically conducted signal to a S input terminal of said flip-flop, such that a Q output terminal of said flip-flop is changed from a low potential voltage to a high potential voltage, and said output driver electrically conducts said power transistor; and

the voltage of said auxiliary winding is fed back to said sample-and-hold circuit to produce a voltage value, and said voltage value and a first voltage reference output an error amplified voltage from said error amplifier, and said error amplified voltage is divided by a plurality of resistors to produce a control voltage, said control voltage is sent to a reverse input terminal of said first comparator;

after said voltage value is stepped down by said voltage divider and said power limit compensation voltage is inputted into said multiplier, the output voltage of said multiplier together with a second voltage reference produces a limit current voltage reference to be sent to a reverse input terminal of said second comparator;

a source voltage of said power transistor is sent to a non-reverse input terminal of said first comparator and a non-reverse input terminal of said second comparator;

if said source voltage is greater than said control voltage or said limit current voltage reference, an OFF signal will be generated and sent from said OR gate to said leading edge blanking circuit to produce a reset signal to a R input terminal of said flip-flop, said reset signal will change the high potential voltage at a Q output terminal of said flip-flop into a low potential voltage, and said output driver drives said power transistor to be off state.

2. The primary-side feedback switching power supply of claim 1, wherein said error amplifier is connected to a compensation component for preventing said error amplifier from being oscillated.

3. The primary-side feedback switching power supply of claim 2, wherein said compensation component is at least one capacitor or at least one capacitor connected to at least one resistor.

4. The primary-side feedback switching power supply of claim 1, wherein said first comparator and said second comparator have non-reverse input terminals connected to a current detection resistor.

5. The primary-side feedback switching power supply of claim 1, wherein the voltage of said power source is divided by a resistor and sent to a reverse input terminal of a subtractor and compared with a third voltage reference to produce said power limit compensation voltage.

6. The primary-side feedback switching power supply having an output current limit of claim 1, further comprising a buffer disposed between said sample-and-hold circuit and said voltage divider.

7. The primary-side feedback switching power supply having an output current limit of claim 1, wherein said sample-and-hold circuit uses a flatter voltage level of a voltage of a voltage feedback input pin after a blank signal to store and track a flatter voltage change, such that if the voltage of said voltage feedback input pin reaches a voltage where a harmonic wave starts turning into another steep slope, the voltage value obtained from said sample-and-hold circuit will immediately stop tracking the voltage change of said voltage feedback input pin, and will store a corner voltage value as a control voltage for controlling an internal voltage regulation and a limit current.