Semiconductor device for rectifying memory defects
First Claim
1. A semiconductor device comprising:
- first memory means including a memory cell and a redundant memory cell;
second memory means for storing an address of a defective memory cell;
rectifier means including replacement means operationally connected to the first memory means;
at least first and second scan chains for writing and storing data of the second memory means; and
a scan chain controller operationally connected to the second memory means,wherein each of the scan chains is operationally connected to the scan chain controller, andwherein the rectifier means is operationally connected to each of the scan chains.
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Abstract
The present invention provides a high-capacity and reliable semiconductor device which does not require additional circuits for use at power ON/OFF, additional steps nor high manufacturing cost, and which has a rectifier means for rectifying a defect easily. A semiconductor device comprises a first memory means including a memory cell and a redundant memory cell each including a memory element in the region where a bit line and a word line cross each other with an insulator interposed therebetween, a second memory means for storing an address of a defective memory in the first memory means, a rectifier means including a holding means and a replacement means, and an inspection means for writing data of the second memory means to the holding means. The replacement means replaces the defective memory cell with the redundant memory cell. In addition to the aforementioned four means, a display means for displaying images is provided as well.
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Citations
8 Claims
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1. A semiconductor device comprising:
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first memory means including a memory cell and a redundant memory cell; second memory means for storing an address of a defective memory cell; rectifier means including replacement means operationally connected to the first memory means; at least first and second scan chains for writing and storing data of the second memory means; and a scan chain controller operationally connected to the second memory means, wherein each of the scan chains is operationally connected to the scan chain controller, and wherein the rectifier means is operationally connected to each of the scan chains. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising:
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a plurality of first memory means each including a plurality of memory cells; second memory means for storing an address of a defective memory cell; a plurality of rectifier means each operationally connected to the first memory means respectively; at least first and second scan chains for writing and storing data of the second memory means; and a scan chain controller operationally connected to the second memory means, wherein at least one of the scan chains is incorporated in a circuit operationally connected to at least one of the plurality of first memory means, wherein each of the scan chains is operationally connected to the scan chain controller, and wherein the rectifier means is operationally connected to each of the scan chains. - View Dependent Claims (6, 7, 8)
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Specification