Semiconductor device for rectifying memory defects

• US 7,239,564 B2
• Filed: 11/17/2004
• Issued: 07/03/2007
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Mutaguchi, Kohei
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): WEINBERG, MICHAEL J
• Application Number:
  US10/989,550
• Publication Number:
  US 20050141264A1
• Time in Patent Office: 958 Days
• Field of Search: 365/200, 365/201, 714/729
• US Class Current: 365/200
• CPC Class Codes: G11C 29/781 combined in a redundant decoder
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

The present invention provides a high-capacity and reliable semiconductor device which does not require additional circuits for use at power ON/OFF, additional steps nor high manufacturing cost, and which has a rectifier means for rectifying a defect easily. A semiconductor device comprises a first memory means including a memory cell and a redundant memory cell each including a memory element in the region where a bit line and a word line cross each other with an insulator interposed therebetween, a second memory means for storing an address of a defective memory in the first memory means, a rectifier means including a holding means and a replacement means, and an inspection means for writing data of the second memory means to the holding means. The replacement means replaces the defective memory cell with the redundant memory cell. In addition to the aforementioned four means, a display means for displaying images is provided as well.

Claims

1. A semiconductor device comprising:

first memory means including a memory cell and a redundant memory cell;

second memory means for storing an address of a defective memory cell;

rectifier means including replacement means operationally connected to the first memory means;

at least first and second scan chains for writing and storing data of the second memory means; and

a scan chain controller operationally connected to the second memory means,

wherein each of the scan chains is operationally connected to the scan chain controller, and

wherein the rectifier means is operationally connected to each of the scan chains.

2. The semiconductor device according to claim 1, wherein the first memory means, the rectifier means, the scan chain controller and the scan chains are formed over the same substrate.

3. The semiconductor device according to claim 1, wherein the first memory means is an SRAM or a DRAM.

4. The semiconductor device according to claim 1, wherein the second memory means is an EPROM, an EEPROM, a flash memory, a mask ROM or a PROM.

5. A semiconductor device comprising:

a plurality of first memory means each including a plurality of memory cells;

second memory means for storing an address of a defective memory cell;

a plurality of rectifier means each operationally connected to the first memory means respectively;

at least first and second scan chains for writing and storing data of the second memory means; and

a scan chain controller operationally connected to the second memory means,

wherein at least one of the scan chains is incorporated in a circuit operationally connected to at least one of the plurality of first memory means,

wherein each of the scan chains is operationally connected to the scan chain controller, and

wherein the rectifier means is operationally connected to each of the scan chains.

6. The semiconductor device according to claim 5, wherein the first memory means, the rectifier means, the scan chain controller and the scan chains are formed over the same substrate.

7. The semiconductor device according to claim 5, wherein the first memory means is an SRAM or a DRAM.

8. The semiconductor device according to claim 5, wherein the second memory means is an EPROM, an EEPROM, a flash memory, a mask ROM or a PROM.