Dedicated processing resources for packet header generation

• US 7,239,630 B1
• Filed: 03/22/2002
• Issued: 07/03/2007
• Est. Priority Date: 03/22/2002
• Status: Expired due to Fees

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Libby, Jeffrey G., Lim, Raymond M.
• Primary Examiner(s): Pham; Chi
• Assistant Examiner(s): Jain; Raj K.
• Application Number:
  US10/102,931
• Time in Patent Office: 1,929 Days
• Field of Search: 370/392, 370/352, 370/353, 370/401, 370/389, 709/236, 709/230
• US Class Current: 370/353
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures

Abstract

A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit may include a single execution section and the L3 generation unit may include multiple parallel execution sections. When both the L2 and L3 generation units complete their operations on a particular packet, a build component combines the generated L2 and L3 information to form a complete packet header.

Claims

1. A packet header processing engine comprising:

a first packet processing unit including at least one execution section configured to generate packet header information relating to a first packet header protocol for a first packet; and

a second packet processing unit implemented in parallel with the first packet processing unit, the second packet processing unit including multiple parallel instruction execution sections configured to generate packet header information relating to a second packet header protocol for the first packet.

2. The packet header processing engine of claim 1, further comprising:

a build component configured to combine the generated packet header information from the first and second packet processing units to form a combined packet header containing the information relating to the first packet header protocol and the second packet header protocol for the first packet.

3. The packet header processing engine of claim 1, wherein the multiple parallel instruction execution sections include three instruction execution sections.

4. The packet header processing engine of claim 3, wherein the at least one instruction execution section is a single instruction execution section.

5. The packet header processing engine of claim 4, wherein the instruction execution sections in the first and second packet processing units are substantially similar instruction execution sections.

6. The packet header processing engine of claim 1, wherein the multiple parallel instruction execution sections execute instructions stored in a corresponding instruction memory.

7. The packet header processing engine of claim 1, wherein the multiple parallel instruction execution sections include a first instruction execution section that controls a single program counter used to index the instruction memory for the multiple parallel instruction execution sections.

8. The packet header processing engine of claim 2, further comprising:

a first output buffer configured to receive the packet header information generated by the first packet processing unit; and

a second output buffer configured to receive the packet header information generated by the second packet processing unit.

9. The packet header processing engine of claim 8, wherein, in forming the combined packet header, the build component unloads the generated packet header information from the first and second output buffers.

10. The packet header processing engine of claim 2, wherein the build component combines the generated packet header information when the first packet processing unit and the second packet processing unit have completed processing of the first and second packet headers, respectively.

11. The packet header processing engine of claim 1, wherein the first packet header protocol is layer 2 (L2) packet processing information.

12. The packet header processing engine of claim 1, wherein the second packet header protocol is layer 3 (L3) packet processing information.

13. The packet header processing engine of claim 1, further comprising:

a memory configured to receive the packet header information relating to the first and second packet header protocols, the memory being coupled to inputs of the first and second packet processing units.

14. A method comprising:

receiving packet header information for a packet;

generating, through the operation of at least one instruction execution section, first protocol information for the packet based on the received packet header information;

generating, through the operation of multiple parallel instruction execution sections, second protocol information for the packet based on the received packet header information; and

forming a combined packet header containing the information relating to the first protocol and the second protocol.

15. The method of claim 14, wherein the multiple parallel instruction execution sections include three instruction execution sections.

16. The method of claim 14, wherein the at least one instruction execution section is a single instruction execution section.

17. The method of claim 14, wherein the instruction execution sections for generating the first and second protocol information are substantially similar instruction execution sections.

18. The method of claim 14, wherein the multiple parallel instruction execution sections execute instructions stored in a corresponding instruction memory.

19. The method of claim 18, wherein the multiple parallel instruction execution sections include a first instruction execution section that controls a single program counter used to index the instruction memory for the multiple parallel instruction execution sections.

20. The method of claim 14, further comprising:

writing the generated first protocol information for the packet to a first buffer; and

writing the generated second protocol information for the packet to a second buffer.

21. The method of claim 14, wherein the first protocol information is level 2 (L2) packet routing information.

22. The method of claim 14, wherein the second protocol information is level 3 (L3) packet routing information.

23. The method of claim 14, wherein the generating the first protocol information and the generating the second protocol information occur concurrently.

24. The method of claim 14, further comprising:

combining the new packet header with non-header information of the packet to form a complete version of the packet.

25. A device comprising:

means for receiving packet header information;

at least one means for generating first protocol information for the packet based on the received packet header information;

means for writing the generated first protocol information for the packet as the first protocol information is generated;

means for generating second protocol information for the packet based on the received packet header information, the means for generating the second protocol information for the packet being implemented in parallel with the at least one means for generating the first protocol information; and

means for writing the generated second protocol information for the packet as the second protocol information is generated.

26. The device of claim 25, wherein the means for writing the generated first protocol information writes the generated first protocol information to a first buffer and the means for writing the second protocol information writes the generated second protocol information to a second buffer.

27. The device of claim 25, wherein the multiple means for generating include three instruction execution sections.

28. The device of claim 25, wherein the at least one means for generating is a single instruction execution section.

29. The device of claim 25, wherein the multiple means for generating execute instructions stored in a corresponding instruction memory.

30. The device of claim 29, wherein the multiple means for generating include a first instruction execution section that controls a single program counter used to index the instruction memory for the multiple parallel instruction execution sections.