System and method for providing a persistent function server

• US 7,240,182 B2
• Filed: 09/16/2004
• Issued: 07/03/2007
• Est. Priority Date: 09/16/2004
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nutter, Mark Richard, Day, Michael Norman, To, VanDung Dang
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/942,432
• Publication Number:
  US 20060095718A1
• Time in Patent Office: 1,020 Days
• Field of Search: 712/34, 709/216, 709/213, 709/211, 709/205, 718/105, 718/106
• US Class Current: 712/34
• CPC Class Codes: G06F 8/52 Binary to binary
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A system and method for providing a persistent function server is provided. A multi-processor environment uses an interface definition language (idl) file to describe a particular function, such as an “add” function. A compiler uses the idl file to generate source code for use in marshalling and de-marshalling data between a main processor and a support processor. A header file is also created that corresponds to the particular function. The main processor includes parameters in the header file and sends the header file to the support processor. For example, a main processor may include two numbers in an “add” header file and send the “add” header file to a support processor that is responsible for performing math functions. In addition, the persistent function server capability of the support processor is programmable such that the support processor may be assigned to execute unique and complex functions.

Claims

1. A computer-implemented method comprising:

retrieving an instruction using a first processor type, the instruction corresponding to a function;

in response to retrieving the instruction, accessing an interface definition language file and locating, within the interface definition file, an instruction identifier that corresponds to the instruction;

in response to locating the instruction identifier in the interface definition language file, selecting a second processor type that is programmed to perform the function, whereby the first processor type and the second processor type share a memory; and

in response to selecting the second processor type, sending a message to the second processor type to execute the function.

2. The method of claim 1 wherein the message includes a pointer that corresponds to a memory location in the shared memory, the memory location including data for use in executing the function.

3. The method of claim 2 wherein the second processor type is adapted to retrieve the data from the memory location and store a result from the function execution in the shared memory.

4. The method as described in claim 3 wherein the second processor type is further adapted to send an acknowledgement to the first processor type wherein the acknowledgement includes the location of the result in the shared memory.

5. The method of claim 1 further comprising:

retrieving the function;

determining that the function should be executed on the second processor type;

in response to determining that the function should be executed on the second processor type, storing the location identifier in the interface definition language file;

compiling the function for use on the second processor type in response to the determination; and

sending the compiled function to the second processor type.

6. The method of claim 1 wherein the message is based upon a function definition included in the interface definition language file.

7. The method of claim 1 wherein the first processor type is a processing unit and the second processor type is a synergistic processing unit.

8. A program product comprising:

computer operable storage medium having computer program code, the computer program code being effective to;

retrieve an instruction using a first processor type, the instruction corresponding to a function;

in response to retrieving the instruction, access an interface definition language file and locating, within the interface definition file, an instruction identifier that corresponds to the instruction;

in response to locating the instruction identifier in the interface definition language file, select a second processor type that is programmed to perform the function, whereby the first processor type and the second processor type share a memory; and

in response to selecting the second processor type, send a message to the second processor type to execute the function.

9. The program product of claim 8 wherein the message includes a pointer that corresponds to a memory location in the shared memory, the memory location including data for use in executing the function.

10. The program product of claim 9 wherein the second processor type is adapted to retrieve the data from the memory location and store a result from the function execution in the shared memory.

11. The program product as described in claim 10 wherein the second processor type is further adapted to send an acknowledgement to the first processor type wherein the acknowledgement includes the location of the result in the shared memory.

12. The program product of claim 8 wherein the computer program code is further effective to:

retrieve the function;

determine that the function should be executed on the second processor type;

in response to determining that the function should be executed on the second processor type, store the location identifier in the interface definition language file;

compile the function for use on the second processor type in response to the determination; and

send the compiled function to the second processor type.

13. The program product of claim 8 wherein the message is based upon a function definition included in the interface definition language file.

14. The program product of claim 8 wherein the first processor type is a processing unit and the second processor type is a synergistic processing unit.

15. An information handling system comprising:

a display;

a plurality of processor types;

a shared memory accessible by the plurality of processor types;

one or more nonvolatile storage devices accessible by the plurality of processor types; and

an instruction management tool for managing application instructions, the instruction management tool comprising software code effective to;

retrieve an instruction from one of the nonvolatile storage devices using a first processor type from the plurality of processor types, the instruction corresponding to a function;

in response to retrieving the instruction, access an interface definition language file from one of the nonvolatile storage devices and locating, within the interface definition file, an instruction identifier that corresponds to the instruction;

in response to locating the instruction identifier in the interface definition language file, select a second processor type from the plurality of processor types that is programmed to perform the function; and

in resronse to selecting the second processor type, send a message over a processor bus to the second processor type to execute the function.

16. The information handling system of claim 15 wherein the message includes a pointer that corresponds to a memory location in the shared memory, the memory location including data for use in executing the function.

17. The information handling system of claim 16 wherein the second processor type is adapted to retrieve the data from the memory location and store a result from the function execution in the shared memory.

18. The information handling system as described in claim 17 wherein the second processor type is further adapted to send an acknowledgement to the first processor type wherein the acknowledgement includes the location of the result in the shared memory.

19. The information handling system of claim 15 wherein the software code is further effective to:

retrieve the function from one of the nonvolatile storage devices;

determine that the function should be executed on the second processor type;

in response to determining that the function should be executed on the second processor type, store the location identifier in the interface definition language file;

compile the function for use on the second processor type in response to the determination; and

send the compiled function to the second processor type over a processor bus.

20. The information handling system of claim 15 wherein the message is based upon a function definition included in the interface definition language file.