Stimulus generation

• US 7,240,260 B2
• Filed: 12/11/2002
• Issued: 07/03/2007
• Est. Priority Date: 12/11/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Mitra, Subhasish, Kim, Kee Sup
• Primary Examiner(s): Lamarre; Guy
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US10/317,605
• Publication Number:
  US 20040117703A1
• Time in Patent Office: 1,665 Days
• Field of Search: 714/726, 714/755, 714/752, 714/33, 714/730, 714/781, 714/782, 714/784, 714/724, 326/16, 324/765
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a respective non-null subset of an input signal set. No two respective stimulus signals in the stimulus signal set may be generated based upon the same respective non-null subset of the input signal set. The stimulus signal set may include a respective number of stimulus signals that is greater than a respective number of input signals in the input signal set. Of course, many modifications, variations, and alternatives are possible without departing from the method of this embodiment.

Claims

1. A method comprising:

generating a stimulus signal set to be supplied, as input, to circuitry, each respective stimulus signal comprised in the stimulus signal set being generated based at least in part upon a respective non-null subset of an input signal set, no two respective stimulus signals comprised in the stimulus signal set being generated based upon the same respective non-null subset of the input signal set, the stimulus signal set comprising a respective number of stimulus signals that is greater than a respective number of input signals comprised in the input signal set.

2. The method of claim 1, wherein:

one or more respective stimulus signals comprised in the stimulus signal set are generated based at least in part upon a result of a respective exclusive-or of two or more respective input signals comprised in the input signal set.

3. The method of claim 1, wherein:

the circuitry comprises a plurality of scan chains, and each of the scan chains is coupled to one respective stimulus signal comprised in the stimulus signal set.

4. The method of claim 3, wherein:

the plurality of scan chains comprises a respective number n of scan chains, and the number n is less than or equal to 2<sup>m−

1</sup>, where m is equal to the respective number of input signals comprised in the input signal set.

5. The method of claim 1, wherein:

each respective non-null subset upon which each respective stimulus signal comprised in the stimulus signal set is based, at least in part, includes a respective odd number of input signals of the input signal set.

6. The method of claim 1, wherein:

each respective non-null subset upon which each respective stimulus signal comprised in the stimulus signal set is based, at least in part, includes a respective odd and equal number of input signals of the input signal set.

7. The method of claim 1, wherein:

an integrated circuit comprises the circuitry and also comprises circuitry to generate, at least in part, the stimulus signal set; and

circuitry external to the integrated circuit generates, at least in part, the input signal set.

8. The method of claim 1, further comprising:

dividing the stimulus signal set into non-null stimulus signal subsets; and

selecting the respective non-null subset of the input signal set upon which each respective stimulus signal in each respective non-null stimulus signal subset is based, at least in part, the selecting of the respective non-null subset of the input signal comprising using, at least in part, one or more error correction and detection code techniques selected from Bose, Chaudhuri, and Hocquenghem and Reed Solomon error correction and detection code techniques.

9. An apparatus comprising:

first circuitry to generate a stimulus signal set to be supplied, as input, to second circuitry, each respective stimulus signal comprised in the stimulus signal set being generated based at least in part upon a respective non-null subset of an input signal set, no two respective stimulus signals comprised in the stimulus signal set being generated based upon the same respective non-null subset of the input signal set, the stimulus signal set comprising a respective number of stimulus signals that is greater than a respective number of input signals comprised in the input signal set.

10. The apparatus of claim 9, wherein:

the first circuitry is capable of generating one or more respective stimulus signals comprised in the stimulus signal set based at least in part upon a result of a respective exclusive-or of two or more respective input signals comprised in the input signal set.

11. The apparatus of claim 9, wherein:

the second circuitry comprises a plurality of scan chains, and each of the scan chains is coupled to one respective stimulus signal comprised in the stimulus signal set.

12. The apparatus of claim 11, wherein:

the plurality of scan chains comprises a respective number n of scan chains, and the number n is less than or equal to 2<sup>m−

1</sup> , where m is equal to the respective number of input signals comprised in the input signal set.

13. The apparatus of claim 9, wherein:

each respective non-null subset upon which each respective stimulus signal comprised in the stimulus signal set is based, at least in part, includes a respective odd number of input signals of the input signal set.

14. The apparatus of claim 9, wherein:

each respective non-null subset upon which each respective stimulus signal comprised in the stimulus signal set is based, at least in part, includes a respective odd and equal number of input signals of the input signal set.

15. The apparatus of claim 9, further comprising:

an integrated circuit that comprises the first circuitry and the second circuitry; and

third circuitry external to the integrated circuit to generate, at least in part, the input signal set.

16. The apparatus of claim 9, wherein:

the stimulus signal set is divided into non-null stimulus signal subsets; and

the respective non-null subset of the input signal set upon which each respective stimulus signal in each respective non-null stimulus signal subset is based, at least in part, is selected using, at least in part, one or more error correction and detection code techniques selected from Bose, Chaudhuri, and Hocquenghem and Reed Solomon error correction and detection code techniques.

17. An article comprising:

a storage medium having stored thereon instructions that when executed by a machine result in the following;

generating a stimulus signal set to be supplied, as input, to circuitry, each respective stimulus signal comprised in the stimulus signal set being generated based at least in part upon a respective non-null subset of an input signal set, no two respective stimulus signals comprised in the stimulus signal set being generated based upon the same respective non-null subset of the input signal set, the stimulus signal set comprising a respective number of stimulus signals that is greater than a respective number of input signals comprised in the input signal set.

18. The article of claim 17, wherein:

one or more respective stimulus signals comprised in the stimulus signal set are generated based at least in part upon a result of a respective exclusive-or of two or more respective input signals comprised in the input signal set.

19. The article of claim 17, wherein:

the circuitry comprises a plurality of scan chains, and each of the scan chains is coupled to one respective stimulus signal comprised in the stimulus signal set.

20. The article of claim 19, wherein:

the plurality of scan chains comprises a respective number n of scan chains, and the number n is less than or equal to 2<sup>m−

1</sup> , where m is equal to the respective number of input signals comprised in the input signal set.

21. The article of claim 17, wherein:

each respective non-null subset upon which each respective stimulus signal comprised in the stimulus signal set is based, at least in part, includes a respective odd number of input signals of the input signal set.

22. The article of claim 17, wherein:

each respective non-null subset upon which each respective stimulus signal comprised in the stimulus signal set is based, at least in part, includes a respective odd and equal number of input signals of the input signal set.

23. The article of claim 17, wherein:

an integrated circuit comprises the circuitry and also comprises circuitry to generate, at least in part, the stimulus signal set; and

circuitry external to the integrated circuit generates, at least in part, the input signal set.

24. The article of claim 17, wherein:

the stimulus signal set is divided into non-null stimulus signal subsets; and

the respective non-null subset of the input signal set upon which each respective stimulus signal in each respective non-null stimulus signal subset is based, at least in part, is selected using, at least in part, one or more error correction and detection code techniques selected from Bose, Chaudhuri, and Hocquenghem and Reed Solomon error correction and detection code techniques.

25. A system comprising:

an integrated circuit comprising first circuitry and second circuitry, the first circuitry being capable of generating a stimulus signal set to be supplied, as input, to the second circuitry, each respective stimulus signal comprised in the stimulus signal set being generated based at least in part upon a respective non-null subset of an input signal set, no two respective stimulus signals comprised in the stimulus signal set being generated based upon the same respective non-null subset of the input signal set, the stimulus signal set comprising a respective number of stimulus signals that is greater than a respective number of input signals comprised in the input signal set.

26. The system of claim 25, further comprising:

third circuitry to receive a first plurality of outputs from the second circuitry, the second circuitry being capable of generating the first plurality of outputs in response at least in part to the stimulus signal set, the third circuitry being capable of generating a second plurality of outputs in response at least in part to the first plurality of outputs, the first plurality of outputs comprising a respective number of outputs that is greater than a respective number of outputs comprised in the second plurality of outputs.

27. The system of claim 26, wherein:

the integrated circuit comprises the third circuitry.

28. The system of claim 26, further comprising:

test input generator circuitry to generate and supply to the first circuitry the input signal set, the test input generator circuitry being external to the integrated circuit.

29. The system of claim 26, further comprising:

test analyzer circuitry to receive the second plurality of outputs.

30. The system of claim 25, wherein:

the first circuitry also is capable of receiving one or more control signals; and

in response at least in part to the one or more control signals, the first circuitry is capable of directly coupling the second circuitry to one or more external terminals of the integrated circuit.

31. The system of claim 30, wherein:

the second circuitry comprises a plurality of scan chains;

the first circuitry is capable of supplying the stimulus signal set to the scan chains;

the one or more control signals indicate, at least in part, which of the scan chains are to be directly coupled by the first circuitry to the one or more external terminals; and

in response at least in part to the one or more control signals, the first circuitry is capable of directly coupling one or more of the scan chains indicated, at least in part, by the one or more control signals to the one or more external terminals.

32. The system of claim 25, wherein:

the second circuitry comprises a plurality of scan chains;

in response at least in part to one or more control signals, the second circuitry is capable of coupling together at least two of the scan chains to form at least one relatively longer scan chain relative to at least one relatively shorter scan chain; and

the first circuitry is capable of supplying to the at least one relatively longer scan chain and the at least one relatively shorter scan chain respective stimulus signals comprised in the stimulus signal set.