Nonplanar device with stress incorporation layer and method of fabrication

• US 7,241,653 B2
• Filed: 06/30/2005
• Issued: 07/10/2007
• Est. Priority Date: 06/27/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jin, Been-Yih, Chau, Robert S., Doyle, Brian S., Hareland, Scott A., Datta, Suman
• Primary Examiner(s): PHAM, HOAI V
• Application Number:
  US11/173,443
• Publication Number:
  US 20050242406A1
• Time in Patent Office: 740 Days
• Field of Search: 438/199, 438/217, 438/218, 438/230, 438/231, 438/300, 438/301, 438/303, 438/758
• US Class Current: 438/199
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

Claims

1. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode on said gate dielectric and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

forming a thin film adjacent to said semiconductor body and beneath said semiconductor body wherein said thin film produces a stress in said semiconductor body.

2. The method of claim 1, wherein said substrate is a semiconductor substrate.

3. The method of claim 1, further comprising forming said thin film on said semiconductor body and directly adjacent to said gate electrode.

4. The method of claim 3, further comprising forming said thin film over said gate electrode.

5. The method of claim 1, said thin film produces a tensile stress in said semiconductor body.

6. The method of claim 1, said thin film produces a compressive stress in said semiconductor body.

7. The method of claim 1, wherein said substrate is an insulating substrate.

8. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a gate dielectric on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

forming a thin film adjacent to said semiconductor body and beneath said semiconductor body wherein said thin film produces a stress in said semiconductor body.

9. The method of claim 8, wherein the substrate is an insulating substrate.

10. The method of claim 9, wherein the insulating substrate comprises an insulating film formed on a silicon substrate, and the insulating film comprises a material selected from the group consisting of silicon dioxide, silicon nitride, nitride, oxide, and sapphire.

11. The method of claim 8, wherein the substrate is a semiconductor substrate comprising a material selected from the group consisting of silicon and gallium arsenide.

12. The method of claim 8, further comprising forming an insulating layer over said top surface of said semiconductor body and beneath said gate electrode formed over said top surface of said semiconductor body.

13. The method of claim 12, wherein the insulating layer comprises silicon nitride.

14. The method of claim 8, wherein said film is to have stress.

15. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a gate dielectric on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode over said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body; and

removing a portion of said substrate underneath said semiconductor body and beneath said gate electrode to expose a portion of said semiconductor body; and

forming an insulating film beneath said exposed portion, said film to produce stress in said semiconductor body beneath said gate electrode.

16. The method of claim 15, wherein forming said film comprises using a vapor deposition technique.

17. The method of claim 15, wherein said film is to produce compressive stress in said semiconductor body beneath said gate electrode.

18. The method of claim 17, wherein said film is to have tensile stress.

19. The method of claim 15, wherein said film is to produce tensile stress in said semiconductor body beneath said gate electrode.

20. The method of claim 19, wherein said film is to have compressive stress.

21. The method of claim 15, wherein said film comprises silicon nitride.

22. The method of claim 15, further comprising oxidizing said exposed portion of said semiconductor body after removing said portion of said substrate and prior to forming said film.

23. A method of forming a semiconductor device comprising:

patterning a monocrystalline silicon film formed on a substrate into a silicon body having a top surface opposite a bottom surface formed on said substrate, and a first and second laterally opposite sidewalls;

forming a gate dielectric layer on said top surface of said silicon body and on said sidewalls of said silicon body;

depositing a gate material over said silicon body and over said substrate;

patterning said gate material to form a gate electrode on said gate dielectric layer on said top surface of said silicon body and adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to said laterally opposite sidewalls of said silicon body;

forming a pair of source/drains regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode, wherein the region between said source/drain regions in said silicon body forms a channel region;

removing a portion of said substrate from underneath a portion of said channel region of said silicon body and beneath a portion of said source and drain regions of said silicon body; and

forming an insulating film beneath said exposed portion of said silicon body beneath said gate electrode and beneath said exposed portion of said source and drain regions beneath said gate electrode, said film to produce stress in said silicon body.

24. The method of claim 23, wherein said insulating film is to produce tensile stress in said channel region.

25. The method of claim 23, wherein said insulating film is to produce compressive stress in said channel region.

26. A method of forming a semiconductor device comprising:

patterning a monocrystalline silicon film formed on a substrate into a silicon body having a top surface opposite a bottom surface formed on said substrate, and a first and second laterally opposite sidewalls;

forming a gate dielectric layer on said sidewalls of said silicon body;

depositing a gate material over said silicon body and over said substrate;

patterning said gate material to form a gate electrode adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to said laterally opposite sidewalls of said silicon body;

forming a pair of source/drains regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode, wherein the region between said source/drain regions in said silicon body forms a channel region;

removing a portion of said substrate from underneath a portion of said channel region of said silicon body and beneath a portion of said source and drain regions of said silicon body; and

forming an insulating film beneath said exposed portion of said silicon body beneath said gate electrode and beneath said exposed portion of said source and drain regions beneath said gate electrode, said film to produce stress in said silicon body.

27. The method of claim 26, wherein said insulating film is to produce tensile stress in said silicon body.

28. The method of claim 26, wherein said insulating film is to produce compressive stress in said silicon body.

29. The method of claim 26, wherein said insulating film is to have stress.

30. The method of claim 26, further comprising forming said insulating film adjacent to said laterally opposite sidewalls of said silicon body and said laterally opposite sidewalls of said gate electrode.