Attachment of integrated circuit structures and other substrates to substrates with vias

• US 7,241,675 B2
• Filed: 03/10/2004
• Issued: 07/10/2007
• Est. Priority Date: 12/17/2003
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Kao, Sam, Savastiouk, Sergey
• Primary Examiner(s): Lindsay, Jr.; Walter
• Assistant Examiner(s): Lee; Kyoung
• Application Number:
  US10/798,540
• Publication Number:
  US 20050136635A1
• Time in Patent Office: 1,217 Days
• Field of Search: 438/106
• US Class Current: 438/597
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad (350) in the substrate but also a surrounding region. Solder (930) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (910.1, 910.2), with the top layer (910.2) being more solder wettable than the bottom layer (910.1) and the top layer covering only a portion of the bottom layer.

Claims

1. A manufacturing method comprising:

forming one or more conductive contact pads in a first substrate at a top surface of the first substrate;

forming dielectric over the top surface, with the dielectric having one or more openings which overlie the contact pads and also overlie one or more regions adjacent to the contact pads;

placing solder paste into the one or more openings; and

heating the solder paste in the one or more openings to melt the solder and to solder one or more contact pads of a second substrate to the one or more contact pads of the first substrate with solder obtained from the solder paste, the dielectric being present over the top surface of the first substrate during soldering.

2. The method of claim 1 wherein the regions adjacent to the contact pads are less solder wettable than the contact pads.

3. The method of claim 1 wherein the regions adjacent to the contact pads are dielectric regions.

4. The method of claim 1 wherein the second substrate is a semiconductor integrated circuit.

5. The method of claim 1 wherein the first substrate is a semiconductor integrated circuit.

6. The method of claim 1 wherein the first substrate is an integrated circuit packaging substrate which does not include a semiconductor substrate.

7. The method of claim 1 wherein the solder paste is placed into the openings to fill the one or more openings.

8. A manufacturing method comprising:

forming one or more conductive contact pads in a first substrate at a top surface of the first substrate, the one or more conductive contact pads including a first contact pad;

forming dielectric over the top surface, with the dielectric having one or more openings, the one or more openings comprising a first opening, wherein each of the contact pads occupies at least a portion of a bottom surface of at least one of the openings, wherein the first contact pad occupies a first portion of the bottom surface of the first opening but does not occupy a second portion of the bottom surface of the first opening;

placing solder paste into the one or more openings; and

heating the solder paste in the one or more openings to melt the solder and to solder one or more contact pads of a second substrate to the one or more contact pads of the first substrate with solder obtained from the solder paste, the dielectric being present over the top surface of the first substrate during soldering.

9. The method of claim 8 wherein the second portion is less solder wettable than the first contact pad.

10. The method of claim 8 wherein the second portion is dielectric.

11. The method of claim 8 wherein the second substrate is a semiconductor integrated circuit.

12. The method of claim 8 wherein the first substrate is a semiconductor integrated circuit.

13. The method of claim 8 wherein the first substrate is an integrated circuit packaging substrate which does not include a semiconductor substrate.

14. The method of claim 8 wherein the solder paste is placed into the openings after the forming of the dielectric over the top surface.

15. A manufacturing method comprising:

forming a first substrate comprising one or more conductive contact pads at a top surface of the first substrate, the one or more conductive contact pads comprising a first contact pad;

forming dielectric on the first substrate, the dielectric having one or more openings, the one or more openings comprising a first opening, wherein each of the contact pads occupies at least a portion of a bottom surface of at least one of the openings, wherein the first contact pad occupies a first portion of the bottom surface of the first opening but does not occupy a second portion of the bottom surface of the first opening;

placing solder on the first substrate, the solder being located in each of the one or more openings, wherein said solder is not placed on the first substrate before the forming of the dielectric on the first substrate;

melting the solder in the one or more openings to solder one or more contact pads of a second substrate to the one or more contact pads of the first substrate with the solder while the dielectric is on the first substrate.

16. The method of claim 15 wherein the solder is placed on the first substrate after the forming of the dielectric on the first substrate.

17. The method of claim 15 wherein placing the solder on the first substrate comprises placing a solder paste containing the solder on the first substrate.

18. The method of claim 15 wherein the second portion is less solder wettable than the first contact pad.

19. The method of claim 15 wherein the second portion is dielectric.

20. The method of claim 15 wherein at least one of the first and second substrates is a semiconductor integrated circuit.

21. A manufacturing method comprising:

forming a first substrate comprising one or more conductive contact pads at a top surface of the first substrate;

forming dielectric on the first substrate, the dielectric having one or more openings which overlie the contact pads;

wherein a top surface of each of the contact pads comprises a first conductive portion and a second conductive portion less solder wettable than the first conductive portion; and

wherein the one or more openings overlie both the first and the second conductive portions of at least one of the contact pads.

22. The method of claim 21 further comprising:

placing solder on the first substrate, the solder being located in each of the one or more openings; and

heating the solder to melt the solder.

23. The method of claim 22 further comprising soldering one or more contact pads of a second substrate to the one or more contact pads of the first substrate with the solder.

24. The method of claim 22 wherein said solder is not placed on the first substrate before the forming of the dielectric on the first substrate.

25. The method of claim 22 wherein the solder is placed on the first substrate after the forming of the dielectric on the first substrate.

26. The method of claim 21 wherein at least one of the first and second substrates is a semiconductor integrated circuit.

27. The method of claim 21 wherein the first substrate is an integrated circuit packaging substrate which does not include a semiconductor substrate.

28. The method of claim 22 wherein:

placing the solder on the first substrate comprises placing solder paste containing the solder into each of the one or more openings;

wherein the method further comprises contacting the solder paste with one or more contact pads of a second substrate; and

wherein heating the solder comprises, after contacting the solder paste with the one or more contact pads of the second substrate, heating the solder paste to melt the solder to solder the one or more contact pads of the second substrate to the one or more contact pads of the first substrate.

29. The method of claim 22 further comprising soldering one or more contact pads of a second substrate to the one or more contact pads of the first substrate with the solder while the dielectric is on the first substrate.