Processing method for protection of backside of a wafer

• US 7,241,693 B2
• Filed: 04/18/2005
• Issued: 07/10/2007
• Est. Priority Date: 04/18/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Huang, Yin-Fu, Lee, Cheng-Hsiung, Lee, Lung-An, Hsu, Chih-Chia, Tseng, Kuo-Pang
• Primary Examiner(s): Wells; Nikita
• Assistant Examiner(s): SOUW, BERNARD E
• Application Number:
  US11/107,885
• Publication Number:
  US 20060234506A1
• Time in Patent Office: 813 Days
• Field of Search: 438/689, 438/702, 438/703
• US Class Current: 438/689
• CPC Class Codes: B81C 1/00896 Temporary protection during separation into individual elements
• CPC Class Codes: B81C 2201/053 Depositing a protective layers
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/3185 of siliconnitrides

Abstract

A temporal protection layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protection layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. With regard to low cost and easy forming and removing, an oxide layer is used as the temporal protection layer. The throughput and yield rate of the wafer production are improved by the use of the temporal protection layer.

Claims

1. A processing method for protection of a backside of a wafer in process of a transferring system;

comprising;

providing said wafer having a topside and said backside opposite thereto, wherein said wafer comprises a semiconductor device region near said topside and said semiconductor device region comprises a IC device region, a dielectric layer and a plurality of conductive structures;

forming a first barrier layer on said backside, wherein said first barrier layer be used as a mask for following process; and

forming a first protective layer on and adjacent to said barrier layer of said backside.

2. The processing method according to claim 1, wherein said step of forming said first barrier layer comprises depositing a low-stress nitride layer.

3. The processing method according to claim 1, wherein said step of forming said first protective layer comprises depositing an oxide layer.

4. The processing method according to claim 1, wherein said step of forming said barrier layer farther deposits a second barrier layer over said semiconductor device region and said topside.

5. The processing method according to claim 4, wherein said step of forming said first protective layer further deposits a second protective layer over said second barrier layer.

6. A processing method for a backside of a silicon wafer for use of micro-electro-mechanical systems (MEMS), comprising:

providing said silicon wafer having a topside and said backside opposite thereto, wherein said silicon wafer comprises a semiconductor device region near said topside and said semiconductor device region comprises a IC device region, a dielectric layer and a plurality of conductive structures;

depositing two silicon nitride layers on said backside and said topside, respectively, wherein said silicon nitride layers be used as a mask for following process; and

depositing an oxide layer on and adjacent to said silicon nitride layer of said backside, whereby protecting said silicon nitride layer of said backside from scratch in process of a transferring system.

7. The processing method according to claim 6, wherein a thickness of said oxide layer on said backside is in the range of 5000 to 10000 Angstroms.

8. The processing method according to claim 6, wherein said step of depositing on said backside is a low-stress silicon nitride layer.

9. The processing method according to claim 6, wherein said oxide layer is formed by a plasma enhanced chemical vapor deposition (PECVD) process.