Lithography device for semiconductor circuit pattern generator

• US 7,242,012 B2
• Filed: 03/07/2003
• Issued: 07/10/2007
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Vanore; David A.
• Application Number:
  US10/385,386
• Publication Number:
  US 20030223535A1
• Time in Patent Office: 1,586 Days
• Field of Search: 250/492.1, 250/492.2, 25049221- 22, 250/505.1, 257/151, 257/619, 257/434, 257/506, 257/419, 257/347, 378/122, 438/157, 438/342, 438/6, 438/107, 438/149, 438/110, 438/25, 438/27, 438/626, 438/667, 430/5, 435/151, 435/158
• US Class Current: 250/492.1
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2203/075 the electronic processing unit being integrated into an element of the micromechanical structure
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 438/949 : Energy beam treating radiation resist on semiconductor

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of making a lithography pattern generation apparatus having an array of exposure cells formed on a substrate, comprising integrating with said array control circuitry for controlling each exposure cell formed on said substrate, and further comprising providing over the substrate at least one elastic dielectric layer.

2. The method of claim 1, wherein each exposure cell comprises means to emit radiation, and the control circuitry controls emission of said radiation.

3. The method of claim 1, wherein each exposure cell comprises an aperture for the passage of radiation and a shutter for occluding the passage of radiation, and the control circuitry controls said passage of radiation.

4. The method of claim 1, further comprising forming at least one demagnifying lens.

5. The method of claim 1, wherein the stress of the at least one elastic dielectric layer is less than about 8×

10⁸ dynes/cm².

6. The method of claim 5, wherein the stress is tensile.

7. The method of claim 1, wherein each cell is formed in an area less than about 50 microns by 50 microns.

8. The device of claim 1, wherein the array of cells includes at least one million cells.

9. The method of claim 1, wherein each exposure cell exposes separate areas of a surface to be exposed.

10. The method of claim 9, wherein the separate areas are substantially non-overlapping.

11. The method of claim 9, wherein substantial portions of the separate areas are exposed simultaneously.

12. The method of claim 1, wherein the stress of the at least one elastic dielectric layer is 2 to 100 times less than the fracture strength of the at least one elastic dielectric layer.

13. The method of claim 12, wherein the stress is tensile.

14. The method of claim 1, wherein the at least one elastic dielectric layer is formed in part from at least one of the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

15. The method of claim 1, further comprising providing at least one thinned flexible substrate that has integrated circuits formed thereon and that is bonded to the lithography pattern generation apparatus.

16. The method of claim 1, further comprising providing at least one thinned flexible substrate that has integrated circuits formed thereon and that overlies the lithography pattern generation apparatus.

17. The method of claims 1, 15, or 16, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

18. A lithography pattern generation device comprising:

an array of cells arranged in rows and columns, the array being formed on a substrate, each cell containing an aperture to permit passage of a radiation from a source and a shutter for occluding the aperture;

control logic integrated with the substrate for at least controlling the operation of each shutter; and

at least one elastic dielectric layer over the substrate.

19. The device of claim 18, wherein the cells expose separate areas of a surface to be exposed.

20. The device of claim 19, wherein the areas are substantially non-overlapping.

21. The device of claim 19, wherein a substantial portion of the separate areas are exposed simultaneously.

22. The device of claim 18, wherein the shutter is implemented by one of a mechanical, electro-static or electro-magnetic means.

23. The device of claim 18, wherein the radiation from a cell is selected from the group consisting of charged particles and electro-magnetic.

24. The device of claim 18, further comprising at least one demagnifying lens.

25. The apparatus of claim 18, wherein the stress of the at least one elastic dielectric layer is less than about 8×

10⁸ dynes/cm².

26. The device of claim 25, wherein the stress is tensile.

27. The device of claim 18, wherein each cell is formed in an area less than about 50 microns by 50 microns.

28. The device of claim 18, wherein the array of cells includes at least one million cells.

29. The device of claim 18, wherein the stress of the at least one elastic dielectric layer is 2 to 100 times less than the fracture strength of the at least one elastic dielectric layer.

30. The device of claim 29, wherein the stress is tensile.

31. The device of claim 18, wherein the at least one elastic dielectric layer is formed in part from at least one of the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

32. The device of claim 18, further comprising at least one thinned flexible substrate that has integrated circuits formed thereon and that is bonded to the lithography pattern generation device.

33. The device of claim 18, further comprising at least one thinned flexible substrate that has integrated circuits formed thereon and that overlies the lithography pattern generation device.

49. The apparatus of claims 18, 34, 32, 33, 47, or 48, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

34. A lithography tool comprising:

an array of radiation source cells with apertures formed on a substrate, each radiation source cell for irradiating areas of a surface to be exposed;

control circuitry integrated with the substrate for individually controlling each radiation source cell; and

at least one elastic dielectric layer.

35. The apparatus of claim 34, wherein the cells expose separate areas of the surface to be exposed.

36. The apparatus of claim 35, wherein the separate areas are substantially non-overlapping.

37. The apparatus of claim 35, wherein a substantial portion of the separate areas are exposed simultaneously.

38. The apparatus of claim 34, wherein the radiation from the source cells is selected from the group consisting of charged particles and electro-magnetic.

39. The apparatus of claim 34, wherein the charged particles are selected from the group consisting of electrons and protons.

40. The apparatus of claim 34, wherein each cell is formed in an area less than about 50 microns by 50 microns.

41. The apparatus of claim 34, wherein the array or radiation source cells includes at least one million cells.

42. The apparatus of claim 34, wherein the stress of the at least one elastic dielectric layer is less than about 8×

10⁸ dynes/cm².

43. The apparatus of claim 42, wherein the stress is tensile.

44. The apparatus of claim 34, wherein the stress of the at least one elastic dielectric layer is 2 to 100 times less than the fracture strength of the at least one elastic dielectric layer.

45. The apparatus of claim 44, wherein the stress is tensile.

46. The apparatus of claim 34, wherein the at least one elastic dielectric layer is formed in part from at least one of the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

47. The apparatus of claim 34, further comprising at least one thinned flexible substrate that has integrated circuits formed thereon and that is bonded to the lithography tool.

48. The apparatus of claim 34, further comprising at least one thinned flexible substrate that has integrated circuits formed thereon and that overlies the lithography tool.

50. A method of making a lithography pattern generation apparatus having an array of exposure cells formed on a substrate, comprising integrating with said array control circuitry for controlling each exposure cell formed on said substrate, further comprising providing over the substrate at least one stress-controlled dielectric layer.

51. The method of claim 50, wherein the stress of the at least one stress-controlled dielectric layer is less than about 8×

10⁸ dynes/cm².

52. The device of claim 51, wherein the stress is tensile.

53. The method of claim 50, wherein the stress of the at least one stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the at least one stress-controlled dielectric layer.

54. The device of claim 53, wherein the stress is tensile.

55. The device of claim 50, wherein the at least one stress-controlled dielectric layer is a flexible dielectric layer.

56. The device of claim 50, wherein the at least one stress-controlled dielectric layer is capable of forming a free standing membrane.

57. The method of claim 50, further comprising forming a plurality of interconnect conductors within the at least one stress-controlled dielectric layer.

58. The method of claim 50, wherein the at least one stress-controlled dielectric layer is formed in part from at least one of the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

59. The method of claim 50, wherein the at least one stress-controlled dielectric layer is formed by at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

60. The method of claim 50, wherein the at least one stress-controlled dielectric layer is formed at a temperature of about 400°

C.

62. The apparatus of claim 60, wherein the stress of the at least one stress-controlled dielectric layer is less than about 8×

10⁸ dynes/cm².

63. The device of claim 62, wherein the stress is tensile.

61. A lithography pattern generation device comprising:

an array of cells arranged in rows and columns, the array being formed on a substrate, each cell containing an aperture to permit passage of radiation from a source and a shutter for occluding the aperture;

control logic integrated with the substrate for at least controlling the operation of each shutter; and

at least one stress-controlled dielectric layer over the substrate.

64. The device of claim 61, wherein the stress of the at least one stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the at least one stress-controlled dielectric layer.

65. The device of claim 64, wherein the stress is tensile.

66. The apparatus of claim 61, wherein the at least one stress-controlled dielectric layer is a flexible dielectric layer.

67. The apparatus of claim 61, wherein the at least one stress-controlled dielectric layer is capable of forming a free standing membrane.

68. The device of claim 61, further comprising a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.

69. The device of claim 61, wherein the at least one stress-controlled dielectric layer is formed in part from at least one of the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

70. The device of claim 61, wherein the at least one stress-controlled dielectric layer is formed by at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

71. The device of claim 61, wherein the at least one stress-controlled dielectric layer is formed at a temperature of about 400°

C.

72. A lithography tool comprising:

an array of radiation source cells with apertures formed on a substrate, each radiation source cell for irradiating areas of a surface to be exposed;

control circuitry integrated with the substrate for individually controlling each radiation source cell; and

at least one stress-controlled dielectric layer.

73. The apparatus of claim 72, wherein the stress of the at least one stress-controlled dielectric layer is less than about 8×

10⁸ dynes/cm².

74. The apparatus of claim 73, wherein the stress is tensile.

75. The apparatus of claim 72, wherein the stress of the at least one stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the at least one stress-controlled dielectric layer.

76. The apparatus of claim 75, wherein the stress is tensile.

77. The apparatus of claim 72, wherein the at least one stress-controlled dielectric layer is a flexible dielectric layer.

78. The apparatus of claim 72, wherein the at least one stress-controlled dielectric layer is capable of forming a free standing membrane.

79. The apparatus of claim 72, further comprising a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.

80. The apparatus of claim 72, wherein the at least one stress-controlled dielectric layer is formed in part from at least one of the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

81. The apparatus of claim 72, wherein the at least one stress-controlled dielectric layer is formed by at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

82. The method of claim 72, wherein the at least one stress-controlled dielectric layer is formed at a temperature of about 400°

C.