Reduced capacitance resistors

• US 7,242,074 B2
• Filed: 12/06/2004
• Issued: 07/10/2007
• Est. Priority Date: 12/06/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Shaw, Jonathan, Nunn, Kevin R., Erickson, Sean C.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US11/005,765
• Publication Number:
  US 20060118908A1
• Time in Patent Office: 946 Days
• Field of Search: 257/532, 257/533, 257536-538
• US Class Current: 257/532
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.

Claims

1. A resistor having reduced parasitic capacitance comprising:

(a) a chosen dielectric material having a first side and a second side;

(b) a first substrate disposed on the first side of said dielectric material and having a surface thereof implanted to a chosen thickness with an effective amount of at least one first dopant, forming thereby a resistive layer having an inter-layer dielectric parasitic capacitance; and

(c) a reverse-biased diode comprising a p-implanted layer formed on an n-well which is formed in a p-type substrate, said p-implanted layer disposed in contact with the second side of said dielectric material, said reversed-biased diode having a capacitance and being series coupled to the inter-layer dielectric parasitic capacitance of said resistive layer.

2. The resistor of claim 1, wherein said p-implanted layer comprises an effective amount of at least one second dopant, and wherein the p-implanted layer is approximately co-extensive with said resistive layer.

3. The resistor of claim 2, wherein said n-well is placed in electrical connection with a ground potential or a chosen voltage.

4. The resistor of claim 2, wherein said n-well and said p-type substrate comprise crystalline silicon.

5. The resistor of claim 4, wherein said at least one second dopant comprises boron.

6. The resistor of claim 1, wherein said first substrate comprises polysilicon.

7. The resistor of claim 1, wherein said at least one first dopant is selected from the group consisting of boron, phosphorus and arsenic.

8. The resistor of claim 1, wherein said dielectric material comprises a low-k dielectric material.

9. The resistor of claim 8, wherein said low-k dielectric material comprises silicon dioxide.

10. The resistor of claim 1, further comprising at least 2 electrical connections on the resistive layer of said first substrate.

11. A method for reducing the parasitic capacitance of a resistor comprising the steps of:

(a) implanting the surface of a first substrate disposed in a chosen dielectric material with an effective amount of at least one first dopant to a chosen depth, forming thereby a resistive layer having a chosen area and having an inter-layer dielectric parasitic capacitance; and

(b) forming a p-type layer on the surface of an n-type substrate, the n-type substrate being disposed within a p-type substrate and spaced apart from the first substrate, wherein the p-type layer has an effective amount of at least one second dopant, wherein the p-type layer is approximately co-extensive with the resistive layer and parallel thereto, and wherein the p-type layer is in contact with the dielectric material, thereby generating a depletion region which behaves as a reversed-biased diode having a capacitance which is series-coupled with the inter-layer dielectric capacitance of the resistive layer.

12. The method of claim 11, further comprising the step of placing the n-type substrate in electrical connection with an electrical ground potential or a chosen voltage, thereby increasing the depletion region.

13. The method of claim 11, wherein the n-type substrate and said p-type substrate comprise crystalline silicon.

14. The method of claim 11, wherein the at least one second dopant comprises boron.

15. The method of claim 11, wherein the dielectric material comprises a low-k dielectric material.

16. The method of claim 15, wherein the low-k dielectric material comprises silicon dioxide.

17. The method of claim 11, further comprising the step of forming electrical connections on the resistive layer.

18. The method of claim 11, wherein the first substrate comprises polysilicon.

19. The method of claim 18, wherein the at least one first dopant is selected from the group consisting of boron, phosphorus and arsenic.

20. A method for reducing the parasitic capacitance of a resistor comprising the steps of:

(a) implanting the surface of a first substrate disposed in a chosen dielectric material with an effective amount of at least one first dopant to a chosen depth, forming thereby a resistive layer having a chosen area and having an inter-layer dielectric parasitic capacitance; and

(b) forming a n-type layer on the surface of a p-type substrate, the p-type substrate being disposed within the dielectric material and spaced apart from the first substrate, wherein the n-type layer has an effective amount of at least one second dopant, wherein the n-type layer is approximately co-extensive with the resistive layer and parallel thereto, and wherein the n-type layer is in contact with the dielectric material, thereby generating a depletion region which behaves as a reversed-biased diode having a capacitance which is series-coupled with the inter-layer dielectric capacitance of the resistive layer.

21. The method of claim 20, further comprising the step of placing the n-type substrate in electrical connection with an electrical ground potential or a chosen voltage, thereby increasing the depletion region.

22. The method of claim 20, wherein the n-type substrate and said p-type substrate comprise crystalline silicon.

23. The method of claim 22, wherein the at least one second dopant is selected from the group consisting of arsenic and phosphorus.

24. The method of claim 20, wherein the first substrate comprises polysilicon.

25. The method of claim 20, wherein the at least one first dopant is selected from the group consisting of boron, phosphorus and arsenic.

26. The method of claim 20, wherein the dielectric material comprises a low-k dielectric material.

27. The method of claim 26, wherein the low-k dielectric material comprises silicon dioxide.

28. The method of claim 20, further comprising the step of forming electrical connections on the resistive layer.