Stacked package structure

• US 7,242,081 B1
• Filed: 04/24/2006
• Issued: 07/10/2007
• Est. Priority Date: 04/24/2006
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lee, Yonggill
• Primary Examiner(s): Andujar; Leonardo
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US11/409,933
• Time in Patent Office: 442 Days
• Field of Search: 257/686, 257/685
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A stacked package structure and a method for manufacturing the same are disclosed. The package structure comprises: a substrate having a first surface and a second surface in opposition to each other; at least one chip deposed on and electrically connected to the first surface of the substrate; a plurality of electrical connection devices deposed on the first surface and periphery of the substrate, wherein each electrical connection device is higher than the at least one chip in altitude; and an encapsulant covering the first surface of the substrate, the at least one chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the encapsulant.

Claims

1. A stacked package structure, comprising:

a first chip package structure comprising;

a first substrate having a first surface and a second surface in opposition to each other;

at least one first chip deposed on and electrically connected to the first surface of the first substrate;

a plurality of first electrical connection devices directly attached to the first surface and periphery of the first substrate, wherein each first electrical connection device is higher than the at least one first chip in altitude, and the first electrical connection devices are a plurality of passive devices;

a first encapsulant covering the first surface of the first substrate, the at least one first chip and the first electrical connection devices, wherein a top end of each first electrical connection device is exposed at a surface of the first encapsulant; and

a plurality of first connections deposed on the second surface of the first substrate, wherein the at least one first chip and the first electrical connection devices are electrically connected to the first connections respectively;

a second chip package structure stacked on the first chip package structure, and the second chip package structure comprising;

a second substrate having a first surface and a second surface in opposition to each other;

at least one second chip deposed on the first surface of the second substrate; and

a second encapsulant covering the first surface of the second substrate and the at least one second chip; and

a plurality of second connections respectively deposed on the top end of each first electrical connection device, and jointed with the second surface of the second substrate, wherein the at least one second chip is electrically connected to the second connections respectively.

2. The stacked package structure according to claim 1, wherein the second chip package structure further comprises a third chip deposed on the second surface of the second substrate.

3. The stacked package structure according to claim 2, wherein a height of each second connection is larger than that of the third chip.

4. The stacked package structure according to claim 1, wherein the second chip package structure further comprises a heat sink deposed on the second surface of the second substrate.

5. The stacked package structure according to claim 1, wherein the first electrical connection devices deposed around the at least one first chip.

6. The stacked package structure according to claim 1, wherein the first chip package structure has the same size as the second chip package structure.

7. A package structure, comprising:

a substrate having a first surface and a second surface in opposition to each other;

at least one chip deposed on and electrically connected to the first surface of the substrate;

a plurality of electrical connection devices directly attached to the first surface and periphery of the substrate, wherein each electrical connection device is higher than the at least one chip in altitude, and the first electrical connection devices are a plurality of passive devices; and

an encapsulant covering the first surface of the substrate, the at least one chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the encapsulant.

8. The package structure according to claim 7, wherein the substrate further comprises a heat sink deposed on the second surface of the substrate.

9. The package structure according to claim 7, wherein the electrical connection devices are deposed around the at least one chip.

10. The package structure according to claim 7, further comprising an electrical component deposed on the package structure, wherein the electrical component is electrically connected to parts of the top ends of the electrical connection devices.