Embedding memory between tile arrangement of a configurable IC

• US 7,242,216 B1
• Filed: 03/15/2005
• Issued: 07/10/2007
• Est. Priority Date: 11/08/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Redgrave, Jason
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US11/081,809
• Time in Patent Office: 847 Days
• Field of Search: 326 38- 41, 326/47, 326/101
• US Class Current: 326/39
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Claims

1. A configurable IC comprising:

a) a plurality of configurable computational tiles and a plurality of memory tiles, said tiles arranged in a particular tile arrangement;

b) each computational tile including a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits, said routing circuits of said tiles for configurably routing signals between configurable logic circuits;

c) a plurality of memory arrays for storing data that serve as variables in the computations of the logic circuits, each memory array embedded in the tile arrangement between two sets of memory tiles;

d) each memory tile including a set of routing circuits;

e) wherein at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

2. The configurable IC of claim 1,

a) wherein each particular computational tile includes a plurality of input-select interconnects, each input-select interconnect for receiving a plurality of signals and supplying a set of the received signals to a logic circuit in the particular computational tile;

b) wherein each particular memory tile includes a plurality of input select interconnects, each input-select interconnect for receiving a plurality of signals and supplying a set of the received signals to the memory array adjacent to the particular memory tile;

c) wherein the first memory tile has the same set of input select interconnects as the second computational tile.

3. The configurable IC of claim 2, wherein two sets of input select interconnects are the same when the two sets includes the same number of input select interconnects and the input select interconnects receives the same number of signals.

4. The configurable IC of claim 3, wherein two sets of interconnects are the same when the relative positions of the interconnects of one set are the same as the relative positions of the interconnects of the other set.

5. The configurable IC of claim 2, wherein the routing circuits within a particular tile connect to the input select interconnects within the particular tile and within other tiles.

6. The configurable IC of claim 5,

a) wherein the routing circuits of the first memory tile have a first set of connections to the input select interconnects of the first tile;

b) wherein the routing circuits of the second computational tile have a second set of connections to the input select interconnects of the second tile, wherein the first and second sets of connections are similar.

7. The configurable IC of claim 1, wherein two sets of routing circuits are the same when the two sets includes the same number of routing circuits and the routing circuits receives the same number of signals.

8. The configurable IC of claim 1, wherein two sets of routing circuits are the same when the relative positions of the routing circuits of one set are the same as the relative positions of the routing circuits of the other set.

9. The configurable IC of claim 1, wherein said routing circuits form a routing network for routing signals between logic circuits and between logic circuits and memory arrays, wherein the embedded memory arrays do not create a discontinuity in the routing network.

10. The configurable IC of claim 9, wherein the routing network in a section about the configurable IC that contains a memory array embedded in a memory tile is the same as the routing network in a section that does not contain the memory array.

11. The configurable IC of claim 1, wherein each set of memory tile includes a plurality of configurable circuits that provide signals to the memory array.

12. The configurable IC of claim 11, wherein the configurable circuits of the two sets of memory tiles form two ports for accessing the memory array.

13. The configurable IC of claim 12, wherein the sets of memory tiles operate based on two different clocks to provide two memory-access ports that operate in two different clock domains.

14. An electronic device comprising:

a configurable IC comprising;

a plurality of configurable computational tiles and a plurality of memory tiles, said tiles arranged in a particular tile arrangement;

each computational tile including a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits, said routing circuits of said tiles for configurably routing signals between configurable logic circuits;

a plurality of memory arrays for storing data that serve as variables in the computations of the logic circuits, each memory array embedded in the tile arrangement between two sets of memory tiles;

each memory tile including a set of routing circuits;

wherein at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

15. The electronic device of claim 14, wherein the configurable IC further comprises:

wherein each particular computational tile includes a plurality of input-select interconnects, each input-select interconnect for receiving a plurality of signals and supplying a set of the received signals to a logic circuit in the particular computational tile;

wherein each particular memory tile includes a plurality of input select interconnects, each input-select interconnect for receiving a plurality of signals and supplying a set of the received signals to the memory array adjacent to the particular memory tile;

wherein the first memory tile has the same set of input select interconnects as the second computational tile.

16. The electronic device of claim 15, wherein two sets of input select interconnects are the same when the two sets includes the same number of input select interconnects and the input select interconnects receives the same number of signals.

17. The electronic device of claim 16, wherein two sets of interconnects are the same when the relative positions of the interconnects of one set are the same as the relative positions of the interconnects of the other set.

18. The electronic device of claim 17, wherein the routing circuits within a particular tile connect to the input select interconnects within the particular tile and within other tiles.

19. The electronic device of claim 18,

a) wherein the routing circuits of the first memory tile have a first set of connections to the input select interconnects of the first tile;

b) wherein the routing circuits of the second computational tile have a second set of connections to the input select interconnects of the second tile, wherein the first and second sets of connections are similar.

20. The electronic device of claim 14, wherein two sets of routing circuits are the same when the two sets includes the same number of routing circuits and the routing circuits receives the same number of signals.

21. The electronic device of claim 14, wherein two sets of routing circuits are the same when the relative positions of the routing circuits of one set are the same as the relative positions of the routing circuits of the other set.

22. The electronic device of claim 14, wherein said routing circuits form a routing network or routing signals between logic circuits and between logic circuits and memory arrays, wherein the embedded memory arrays do not create a discontinuity in the routing network.

23. The electronic device of claim 22, wherein the routing network in a section about the configurable IC that contains a memory array embedded in a memory tile is the same as the routing network in a section that does not contain the memory array.