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I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures

  • US 7,243,175 B2
  • Filed: 03/02/2004
  • Issued: 07/10/2007
  • Est. Priority Date: 12/20/1996
  • Status: Expired due to Fees
First Claim
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1. An arrangement, comprising:

  • a processor including a plurality of cells configurable with regard to at least one of function and interconnections;

    at least one memory,an address arrangement configured to address the at least one memory; and

    an internal global bus system communicatively coupled to the address arrangement, the plurality of cells being connectable via the internal global bus system;

    wherein the address arrangement is further configured to indicate an end of a data transfer via a signal on a bus.

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