I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures

• US 7,243,175 B2
• Filed: 03/02/2004
• Issued: 07/10/2007
• Est. Priority Date: 12/20/1996
• Status: Expired due to Fees

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, Munch, Robert
• Primary Examiner(s): Ray; Gopal C.
• Application Number:
  US10/792,168
• Publication Number:
  US 20040199688A1
• Time in Patent Office: 1,225 Days
• Field of Search: 710/100, 710/300, 710/8, 710/72, 710/305, 712/11, 712/14, 712/18, 716/16, 716/17, 326/38, 326/39, 326/41, 439/68
• US Class Current: 710/100
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Claims

1. An arrangement, comprising:

a processor including a plurality of cells configurable with regard to at least one of function and interconnections;

at least one memory,

an address arrangement configured to address the at least one memory; and

an internal global bus system communicatively coupled to the address arrangement, the plurality of cells being connectable via the internal global bus system;

wherein the address arrangement is further configured to indicate an end of a data transfer via a signal on a bus.

2. The arrangement according to claim 1, wherein the address arrangement is an address generator.