On-chip inter-subsystem communication
First Claim
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1. A data transfer block for use in an integrated circuit (IC) to interface an on-chip subsystem to an on-chip bus, the data transfer block comprising:
- a first and a second outbound queue to facilitate staging of a first and a second plurality of outbound bus transactions for the on-chip subsystem, each of said outbound bus transactions including a bus arbitration priority; and
a first state machine coupled to the first and second outbound queues to service the first and second outbound queues by according the first queue a first outbound priority and the second queue a second outbound priority, and requesting for access to the on-chip bus for the staged outbound bus transactions based at least in part on accorded outbound priorities, where access to the on-chip bus is granted to requesting bus transactions based at least in part on the included bus arbitration priorities of the contending bus transactions.
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Abstract
A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.
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Citations
14 Claims
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1. A data transfer block for use in an integrated circuit (IC) to interface an on-chip subsystem to an on-chip bus, the data transfer block comprising:
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a first and a second outbound queue to facilitate staging of a first and a second plurality of outbound bus transactions for the on-chip subsystem, each of said outbound bus transactions including a bus arbitration priority; and a first state machine coupled to the first and second outbound queues to service the first and second outbound queues by according the first queue a first outbound priority and the second queue a second outbound priority, and requesting for access to the on-chip bus for the staged outbound bus transactions based at least in part on accorded outbound priorities, where access to the on-chip bus is granted to requesting bus transactions based at least in part on the included bus arbitration priorities of the contending bus transactions. - View Dependent Claims (2, 3, 4)
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5. A data transfer block for use in an integrated circuit (IC) to interface an on-chip subsystem to an on-chip bus, the data transfer block comprising:
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a first and a second inbound queue to facilitate staging of a first and a second plurality of inbound bus transactions for the on-chip subsystem, each of the inbound bus transactions including a bus arbitration priority and being granted access to the on-chip bus based at least in part on the included bus arbitration priority; and a state machine coupled to the first and second inbound queues to service the first and second inbound queues by according the first inbound queue a first inbound priority and the second inbound queue a second inbound priority and bringing the staged inbound bus transactions to the attention of the on-chip subsystem based at least in part on the accorded inbound priorities. - View Dependent Claims (6)
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7. A subsystem of an integrated circuit, the subsystem comprising:
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core subsystem logic; and a data transfer unit to couple the core subsystem logic to an on-chip bus of the integrated circuit, the data transfer unit including; a first and a second outbound queue to facilitate staging of a first and a second plurality of outbound bus transactions for the core subsystem logic, each of said outbound bus transactions including a bus arbitration priority; and a first state machine coupled to the first and second outbound queues to service the first and second outbound queues by according the first queue a first outbound priority and the second queue a second outbound priority, and requesting for access to the on-chip bus for the staged outbound bus transactions based at least in part on accorded outbound priorities, where access to the on-chip bus is granted to requesting bus transactions based at least in part on the included bus arbitration priorities of the contending bus transactions. - View Dependent Claims (8, 9, 10, 11)
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12. A subsystem of an integrated circuit, the subsystem comprising:
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core subsystem logic; and a data transfer unit to couple the core subsystem logic to an on-chip bus of the integrated circuit, the data transfer unit including; a first and a second inbound queue to facilitate staging of a first and a second plurality of inbound bus transactions for the core subsystem logic, each of the inbound bus transaction including a bus arbitration priority and being granted access to the on-chip bus based at least in part on the included bus arbitration priority; and a state machine coupled to the first and second inbound queues to service the first and second inbound queues by according the first inbound queue a first inbound priority and the second inbound queue a second inbound priority and bringing the staged inbound bus transactions to the attention of the on-chip subsystem based at least in part on the in bound priority. - View Dependent Claims (13, 14)
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Specification