Memory testing device and method

• US 7,243,273 B2
• Filed: 06/13/2002
• Issued: 07/10/2007
• Est. Priority Date: 04/24/2002
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lin, Wen-Hsi
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US10/172,454
• Publication Number:
  US 20030204797A1
• Time in Patent Office: 1,853 Days
• Field of Search: 714/718, 714/719, 714/720, 714/736, 714/738, 702/117, 365/201, 365/230.03
• US Class Current: 714/718
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A memory testing apparatus rapidly tests memory devices with a relatively small error catch memory. The memory testing apparatus provides an address compressing module that minimizes an amount of error catch memory necessary to test one or more memory devices. The memory testing apparatus further divides each of the memory devices into a plurality of areas, and tests each area sequentially until a bit failure is detected in the area thereby attenuating testing time.

Claims

1. A memory testing apparatus for testing a plurality of areas of memory cells of a first memory device and a second memory device, comprising:

a waveform-shaping module configured to generate a plurality of test signals according to a plurality of address signals and to output each of the plurality of test signals to one of the memory devices;

a comparing module configured to compare expected values corresponding to the test signals with output signals from corresponding memory devices of the first memory device and the second memory device in response to the plurality often signals, and to output a plurality of comparison results;

an address-compressing module configured to generate compressed addresses for the plurality of comparison results; and

an error catch memory configured to record outputted comparison results for both the first memory device and the second memory device in a corresponding plurality of consecutive divisions of the error catch memory according to a corresponding plurality of the compressed addresses for the first memory device and the second memory device, each of the outputted comparison results being stored as a single bit;

wherein the memory testing apparatus is configured to test all areas of the plurality of areas and not to test all memory cells in a given area when any comparison result is indicative of a failed memory cell in that area.

2. The memory testing apparatus of claim 1, wherein the compressed address points to a bit of the error catch memory.

3. The memory testing apparatus of claim 1, wherein:

the test signal comprises a data signal;

the output signal corresponds to an area of the memory device that was written with the data signal and then read from; and

the compressed address maps the area of the memory device to an area of the error catch memory.

4. The memory testing apparatus of claim 3, wherein:

the area of the memory device comprises a plurality of bits; and

the area of the error catch memory is one bit.

5. The memory testing apparatus of claim 1, wherein:

the compressed address maps an area of the memory device to an area of the error catch memory; and

the area of the memory device is greater than the area of the error catch memory.

6. The memory testing apparatus of claim 5, wherein:

the area of the memory device comprises a plurality of bits; and

the area of the error catch memory is one bit.

7. The memory testing apparatus of claim 1, wherein:

the test signal comprises a data signal which is equal to the expected value;

a number of bits of the data signal is equal to a number of bits of the output signal; and

the comparing module is configured to sequentially compare bits of the output signal with corresponding bits of the expected value, the comparing module being configured to stop comparing the bits of the output signal and the expected value when a mismatch is detected between a bit of the output signal and a corresponding bit of the expected value, the mismatch indicating a failed memory location of the memory device.

8. The memory resting apparatus of claim 1, wherein the error catch memory is configured to record the comparison result in a memory location of the error catch memory according to the compressed address only when the comparison result is indicative of a mismatch between the output signal and the expected value.

9. The memory testing apparatus of claim 1, wherein:

the test signal includes the expected value;

the address compressing module uses the address signal to generate the compressed address;

the memory testing apparatus further comprises a pattern-generating module that is configured to generate and output the address signal and the expected value;

the address signal points to a cell area of the memory device;

when one or more bits of the expected value and the output signal are mismatched, the comparing module stops comparing and outputs the comparison result as a “

fail”

; and

when the expected value and the corresponding output signal are matched, the comparing module outputs the comparison result as a “

pass.”

10. The memory testing apparatus of claim 1, wherein the memory testing apparatus is configured not to test all memory cells in a given area, and to skip testing of memory cells in an adjacent area, when any comparison result is indicative of a failed memory cell in the given area.

11. A memory testing apparatus for testing a plurality of areas of memory cells of at least one memory device, comprising:

a waveform-shaping module configured to generate a test signal according to an address signal and to output the test signal to the memory device;

a comparing module configured to compare an expected value with an output signal received from the memory device in response to the test signal, and to output a comparison result;

an address-compressing module configured to generate a compressed address for the comparison result; and

an error catch memory configured to record the comparison result in a memory location of the error catch memory according to the compressed address;

wherein the memory testing apparatus is configured to test all areas of the plurality of areas and not to rest all memory cells in a given area upon a comparison result is indicative of a failed memory cell in that area;

wherein the at least one memory device includes a first memory device and a second memory device; and

wherein the error catch memory comprises a plurality of consecutive divisions, each division storing comparison results indicative of failed areas of a given one of the memory devices and each comparison result being stored as a single bit.

12. A memory testing apparatus for testing a plurality of areas of memory locations of a first memory device and a second memory device, the memory testing apparatus testing the first and second memory devices in parallel and comprising:

a waveform-shaping module configured to generate a plurality of test signals, the test signals comprising a plurality of address signals and a plurality of expected values, each of the plurality of address signals pointing to an area of a corresponding one of the memory devices, the waveform-shaping module further being configured to output a the test signals to the memory devices in parallel so that the memory devices are tested in parallel; and

a comparing module configured to sequentially compare bits of output signals, received from the memory devices in response to the test signals, with corresponding bits of expected values, the comparing module being configured to output comparison results and further being configured to stop comparing the bits of the output signals and the expected values when a any mismatch is detected between a bit of an output signal and a corresponding bit of an expected value, the mismatch indicating a failed memory location of a memory device;

wherein the comparing module is configured to compare the expected values with output signals from the memory devices, which are received from the memory devices in response to the test signals, and the comparing module being configured to output comparison results;

wherein the memory testing apparatus further comprises an address-compressing module that is configured to generate compressed addresses for the comparison results, using corresponding address signals; and

wherein the memory testing apparatus further comprises an error catch memory that is configured to receive comparison results for the memory devices and record tern in a plurality of consecutive divisions of the error catch memory according to a corresponding plurality of the compressed addresses, each division storing comparison results indicative of failed areas of a given one of the memory devices and each of the comparison results being stored as a single bit.

13. The memory testing apparatus of claim 12, wherein, following detection of a mismatch, the waveform-shaping module outputs another test signal to the memory device, and the comparing module sequentially compares bits of another output signal, received from the memory device in response to the other test signal, with corresponding bits of another expected value.

14. The memory testing apparatus of claim 13, wherein:

the test signal includes an address signal tat points to a cell area of the memory device; and

following the detection of a mismatch, the address signal is changed to point to another cell area of the memory device.

15. The memory testing apparatus of claim 14, wherein:

the comparing module is configured to output a comparison result upon detection of a mismatch; and

the memory testing apparatus further comprises;

(a) an address-compressing module configured to generate a compressed address for the comparison result; and

(b) an error catch memory configured to record the comparison result in a memory location of the error catch memory according to the compressed address.

16. The memory testing apparatus of claim 15, wherein:

the compressed address points to a bit of the error catch memory; and

the comparison result is stored in the bit of the error catch memory.

17. The memory testing apparatus of claim 16, wherein:

the memory device comprises a plurality of cell areas, with each cell area comprising a plurality of bits; and

a number of bits of the expected value is equal to a number of bits of the output signal.

18. The memory testing apparatus of claim 12, wherein the memory testing apparatus is configured not to test all memory locations in a given area of the plurality of areas, and to skip testing of memory locations in an adjacent area of the plurality of areas, upon any detection of a mismatch indicative of a failed memory location in the given area.

19. A memory testing method for testing a plurality of areas of memory cells of a first memory device and a second memory device, comprising:

generating a plurality of test signals according to a plurality of address signals;

outputting in a parallel fashion each of the plurality of test signals to the memory devices so that the memory devices are tested in parallel;

comparing expected values corresponding to the test signals with output signals from corresponding memory devices in response to the test signals;

outputting comparison results corresponding to the memory devices;

generating compressed addresses for the comparison results; and

recording the comparison results for the memory devices in consecutive divisions of an error catch memory according to the compressed addresses, each division storing comparison results indicative of failed areas of a given one of the memory devices and each comparison result being stored as a single bit wherein all areas of the plurality of areas are tested but not all memory cells in a given area are tested upon any occurrence of a comparison result indicative of a failed memory cell in that area.

20. The memory testing method of claim 19, wherein

the test signal comprises a data signal;

the output signal corresponds to an area of the memory device that was written with the data signal and then read from; and

the compressed address maps the area of the memory device to an area of the error catch memory, which is smaller than the area of the memory device.

21. The memory testing method of claim 19, wherein:

the test signal comprises a data signal which is equal to the expected value;

a number of bits of the data signal is equal to a number of bits of the output signal; and

the comparing includes sequentially comparing bits of the output signal with corresponding bits of the expected value, until (1) all bits of the output signal have been compared or (2) a mismatch is detected between a bit of the output signal and a corresponding bit of the expected value, the mismatch indicating a failed memory location of the memory device.

22. The memory testing method of claim 19, wherein the error catch memory records the comparison result in a memory location of the error catch memory according to the compressed address only when the comparison result is indicative of a mismatch between the output signal and the expected value.

23. The memory resting method of claim 19, wherein:

the test signal includes the expected value;

the address signal is used to generate the compressed address;

the address signal points to a cell area of the memory device;

when the expected value and the corresponding output signal are mismatched, the comparing stops and a “

fail”

comparison result is outputted; and

when the expected value and the corresponding output signal are matched, a “

pass”

comparison result is outputted.

24. The memory testing method of claim 19, wherein testing of memory cells in an area adjacent to the given area is skipped upon any occurrence of a comparison result indicative of a failed memory cell in the given area.

25. A memory testing method for testing a plurality of areas of memory locations of a plurality of memory devices, wherein the plurality of memory devices are tested in parallel, the memory testing method comprising:

generating a plurality of test signals, the test signals comprising a plurality of address signals and a plurality of expected values, each of the plurality of address signals pointing to an area of a corresponding one of the memory devices;

outputting in parallel the test signals to the memory devices;

sequentially comparing bits of output signals, received from each of the memory devices in response to the test signals, with corresponding bits of expected values, the comparing of bits of the output signals and the expected values being halted for any one of the memory devices being tested in parallel when any occurrence of a mismatch is detected between a bit of an output signal and a corresponding bit of an expected value, the mismatch indicating a failed memory location of the corresponding memory device; and

recording comparison results for the memory devices in a corresponding plurality of memory locations of an error catch memory, wherein the error catch memory comprises a plurality of consecutive divisions, each division storing comparison results indicative of failed areas of a given one of the memory devices and each comparison result being stored as a single bit.

26. The memory testing method of claim 25, wherein following detection of a mismatch, another test signal is outputted to the memory device, and bits of another output signal, which is received from the memory device in response to the other test signal, are sequentially compared with corresponding bits of another expected value.

27. The memory testing method of claim 26, and further comprising:

outputting a comparison result upon detection of a mismatch;

generating a compressed address for the comparison result; and

recording the comparison result in a memory location of an error catch memory according to the compressed address.

28. The memory testing method of claim 27, wherein:

the memory device comprises a plurality of cell areas, with each cell area comprising a plurality of bits;

the compressed address points to a bit of the error catch memory; and

the comparison result is stored in the bit of the error catch memory.

29. The memory testing method of claim 25, wherein the at least one memory device includes a first memory device and a second memory device, and wherein:

the comparing is followed with outputting comparison results;

the memory testing method includes generating compressed addresses for the comparison results, using corresponding address signals; and

the memory testing method further includes recording comparison results fur the first memory device and the second memory device in a corresponding plurality of memory locations of an error catch memory according to a corresponding plurality of the compressed addresses.

30. The memory testing method of claim 25, wherein:

the mismatch indicates a failed memory location of a given area of the memory device; and

testing of memory locations in an area adjacent to the given area is skipped upon any detection of a mismatch indicative of a failed memory location in the given area.