System and method for communicating image data using error correction coding

• US 7,243,291 B1
• Filed: 04/30/2002
• Issued: 07/10/2007
• Est. Priority Date: 04/30/2002
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Williams, Robert A.
• Primary Examiner(s): Torres, Joseph D.
• Application Number:
  US10/137,026
• Time in Patent Office: 1,897 Days
• Field of Search: 714/776, 714/758
• US Class Current: 714/776
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 2370/04 Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A method for communicating video data is provided that includes generating a plurality of error correction code bits and positioning the error correction code bits in a stream of image data such that the stream of image data is encoded. The stream of image data may then be received and encoded in order to convert the stream of image data into a digital visual interface (DVI) format. The stream of image data may then be decoded such that the stream of image data may be displayed in the DVI format. The stream of image data may then be received and checked for one or more errors using the error correction code bits.

Claims

1. An apparatus for communicating image data, the apparatus comprising:

an error correction coding (ECC) encoder operable to generate a plurality of error correction code bits, the ECC encoder positioning the error correction code bits in a stream of image data such that the stream of image data is encoded, the stream of image data being carried over a plurality of channels;

a digital visual interface (DVI) encoder coupled to the ECC encoder and operable to receive the stream of image data from the ECC encoder and to encode the stream of image data in order to convert each channel of the stream of image data into a DVI format, the plurality of channels including a plurality of data channels each carrying a plurality of data bits and an ECC channel carrying the plurality of error correction code bits, each of the plurality of error correction code bits being generated by the ECC encoder using various combinations of a plurality of data bits from each of the plurality of data channels whereby each error correction code bit is generated from groups of bits selected from the plurality of data bits for each channel, and whereby each group comprises various bits selected from the plurality of data bits for each of the data channel.

2. The apparatus of claim 1, further comprising:

an additional DVI encoder coupled to the ECC encoder and operable to receive a portion of the stream of image data, the additional DVI encoder being further operable to encode the portion of the stream of image data in order to convert the portion of the stream of image data into the DVI format.

3. The apparatus of claim 1, further comprising:

a DVI decoder operable to receive the stream of image data from the DVI encoder and to decode the stream of image data such that the stream of image data may be displayed in the DVI format; and

an ECC decoder operable to receive the stream of image data from the DVI decoder and to check the stream of image data for one or more errors using the error correction code bits, the ECC decoder being further operable to decode the stream of image data such that the stream of image data may be communicated to a next destination after it is checked.

4. The apparatus of claim 3, further comprising:

a video processing element operable to receive the stream of image data from the ECC decoder and to process the stream of image data, wherein the stream of image data is checked by the ECC decoder for one or more errors by executing a parity check that uses the error correction code bits.

5. The apparatus of claim 4, further comprising:

a monitor operable to receive the stream of image data from the video processing element and to display an image based on the stream of image data.

6. The apparatus of claim 3, further comprising:

a first field programmable gate array (FPGA), the FPGA including the ECC encoder and the DVI encoder;

a second FPGA coupled to the FPGA, the additional FPGA including the DVI decoder and the ECC decoder.

7. The apparatus of claim 1, further comprising:

a video source coupled to the ECC encoder and operable to communicate the stream of image data to the ECC encoder, wherein the stream of image data comprises pixel data.

8. The apparatus of claim 1, further comprising:

an alpha channel coupled to the ECC encoder and operable to facilitate propagation of the error correction code bits along the alpha channel.

9. A method for communicating image data, the method comprising:

generating a plurality of error correction code bits;

positioning the error correction code bits in a stream of image data such that the stream of image data is encoded, the stream of image data being carried over a plurality of channels;

receiving the stream of image data and encoding the stream of image data in order to convert each channel of the stream of image data into a digital visual interface (DVI) format, the plurality of channels including a plurality of data channels each carrying a plurality of data bits and an ECC channel carrying the plurality of error correction code bits, each of the plurality of error correction code bits being generated using various combinations of a plurality of data bits associated with each of the plurality of data channels whereby each error correction code bit is generated from groups of bits selected from the plurality of data bits for each channel, and whereby each group comprises various bits selected from the plurality of data bits for each of the data channels.

10. The method of claim 9, further comprising:

receiving a portion of the stream of image data; and

encoding a portion of the stream of image data in order to convert the portion of the stream of image data into the DVI format.

11. The method of claim 9, further comprising:

decoding the stream of image data such that it may be displayed in the DVI format; and

receiving the stream of image data and checking the stream of image data for one or more errors using the error correction code bits.

12. The method of claim 11, wherein the stream of image data is checked for one or more errors by executing a parity check that uses the error correction code bits, and wherein the stream of image data comprises pixel data.

13. The method of claim 11, further comprising:

receiving the stream of image data after it is processed; and

displaying an image that is based on the stream of image data.

14. The method of claim 9, further comprising:

communicating the error correction code bits along an alpha channel such that the error correction code bits may be positioned in the stream of image data and the stream of image data may be encoded.

15. A computer readable medium having code for communicating image data, the code operable to:

generate a plurality of error correction code bits;

position the error correction code bits in a stream of image data such that the stream of image data is encoded, the stream of image data being carried over a plurality of channels;

receive the stream of image data and encode the stream of image data in order to convert each channel of the stream of image data into a digital visual interface (DVI) format, the plurality of channels including a plurality of data channels each carrying a plurality of data bits and an ECC channel carrying the plurality of error correction code bits, each of the plurality of error correction code bits being generated using various combinations of a plurality of data bits associated with each of the plurality of data channels whereby each error correction code bit is generated from groups of bits selected from the plurality of data bits for each channel, and whereby each group comprises various bits selected from the plurality of data bits for each of the data channels.

16. The code of claim 15, further operable to:

receive a portion of the stream of image data; and

encode a portion of the stream of image data in order to convert the portion of the stream of image data into the DVI format.

17. The code of claim 15, further operable to:

decode the stream of image data such that it may be displayed in the DVI format; and

receive the stream of image data and check the stream of image data for one or more errors using the error correction code bits.

18. The code of claim 17, wherein the stream of image data is checked for one or more errors by executing a parity check that uses the error correction code bits, and wherein the stream of image data comprises pixel data.

19. The code of claim 17, further operable to:

process the stream of image data in order to enhance image resolution associated with the stream of image data; and

display an image that is based on the stream of image data.

20. The code of claim 15, further operable to:

communicate the error correction code bits along an alpha channel such that the error correction code bits may be positioned in the stream of image data and the stream of image data may be encoded.