Method for filling recessed micro-structures with metallization in the production of a microelectronic device

• US 7,244,677 B2
• Filed: 02/04/1998
• Issued: 07/17/2007
• Est. Priority Date: 02/04/1998
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Semitool Incorporated (Applied Materials Incorporated)
• Inventors: Ritzdorf, Thomas L., Graham, Lyndon W.
• Primary Examiner(s): Nadav; Ori
• Application Number:
  US09/018,783
• Publication Number:
  US 20020022363A1
• Time in Patent Office: 3,450 Days
• Field of Search: 438/687,597,637,672,678
• US Class Current: 438/687
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: C25D 5/18 Electroplating using modulated, pulsed or reversing current
• CPC Class Codes: C25D 5/50 by heat-treatment
• CPC Class Codes: C25D 5/605 Surface topography of the layers, e.g. rough, dendritic or nodular layers
• CPC Class Codes: C25D 5/611 Smooth layers
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.

Claims

1. A method for filling recessed microstructures at a surface of a semiconductor workpiece having a barrier layer with a continuous non-alloyed copper seed layer on the barrier layer, the method comprising:

depositing copper into contact with the seed layer to form continuous copper in the recessed micro-structures using an electrochemical plating process that generates copper grains that are sufficiently small so as to substantially fill the recessed microstructures; and

subjecting the surface of the semiconductor workpiece with the deposited copper to an elevated temperature annealing process at a temperature above an ambient temperature and below about 100 degrees Celsius for a time period that is sufficient to increase the grain size of the deposited copper.

2. A method as claimed in claim 1 wherein an electroplating waveform is used, at least in part, to ensure the sufficiently small copper grain size generation within the recessed microstructures.

3. A method as claimed in claim 1 wherein an electroplating solution additive is used, at least in part, to ensure the sufficiently small copper grain size generation within the recessed microstructures.

4. A method for filling recessed microstructures at a surface of a semiconductor workpiece having a barrier layer with a continuous non-alloyed copper seed layer on the barrier layer, the method comprising:

depositing copper into contactwith the seed layer to form ocntinuous copper in the recessed microstructures using an electrochemical plating process that generates copper grains that are sufficiently small so as to substantially fill the recessed microstructures; and

subjecting the surface of the semiconductor workpiece and the deposited copper to an elevated temperature annealing process at a temperature above an ambient temperature and at or below about 250 degrees Celsius for a time period of no longer than 15 minutes, which time period is sufficient to increase the grain size of the deposited copper.

5. A method as claimed in claim 4 wherein an electroplating waveform is used, at least in part, to ensure the sufficiently small metal grain size.

6. A method as claimed in claim 4 wherein an electroplating solution additive is used, at least in part, to ensure the sufficiently small metal grain size.

7. A method for filling recessed microstructures at a surface of a semiconductor workpiece, the workpiece including at least one low-K dielectric layer, a barrier layer on the dielectric layer and a continuous non-alloyed copper seed layer on the barrier layer, the method comprising:

depositing copper into contact with the seed layer to form continuous copper in the recessed micro-structures using an electrochemical plating process that generates copper grains that are sufficiently small so as to substantially fill the recessed microstructures; and

subjecting the surface of the semiconductor workpiece with the deposited copper to an elevated temperature annealing process at a temperature selected to be above an ambient temperture and below a predetermined temperature at which the low-K dielectric layer would suffer substantial degradation.

8. A method for filling recessed microstructures at a surface of a semiconductor workpiece with copper metal comprising:

providing a semiconductor workpiece with a feature that is to be connected with copper metallization;

applying at least one low-K dielectric layer over a surface of the semiconductor workpiece including the feature;

providing recessed microstructures in the at least one dielectric layer;

preparing a surface of the workpiece including the recessed microstructures with a barrier layer and a non-alloyed continuous copper seed layer for subsequent electrochemical copper deposition;

electrochemically plating a copper layer onto the seed layer to form continuous copper in the recessed microstructures with copper grains that are sufficiently small to substantially fill the recessed microstructures;

annealing the electrochemically deposited copper for a predetermined period of time at an elevated temperature selected to be above an ambient temperature and below a predetermined temperature at which the low-K dielectric layer would substantially degrade; and

removing copper metallization from the surface of the workpiece except from the recessed microstructures, after the annealing of the copper.

9. A method as claimed in claim 8 wherein the step of preparing a surface of the workpiece comprises:

applying at least one barrier layer over the dielectric layer; and

applying a metal seed layer over the barrier layer.

10. A method as claimed in claim 9 wherein the step of applying the seed layer is defined by applying the seed layer using a chemical vapor deposition process.

11. A method as claimed in claim 9 wherein the step of applying the seed layer is defined by applying the seed layer using a physical vapor deposition process.

12. A method as claimed in claim 8 wherein the step of preparing a surface of the workpiece comprises:

applying at least one adhesion layer over the dielectric layer; and

applying a metal seed layer over the adhesion layer.

13. A method as claimed in claim 8 wherein the step of removing the copper metallization is defined by removing the copper metallization using a chemical mechanical polish technique.

14. A method for filling recessed microstructures at a surface of a semiconductor workpiece with copper metal comprising:

providing a semiconductor workpiece with a feature that is to be connected with copper metallization;

applying at least one dielectric layer over a surface of the semiconductor workpiece including the feature;

providing recessed microstructures in the at least one dielectric layer;

preparing a surface of the workpiece, including the recessed microstructures, with a barrier layer and a continuous non-alloyed copper seed layer for subsequent electrolytic copper deposition;

electrolytically depositing copper onto the continuous copper seed layer to form continuous copper within the microstructures with copper grains that are sufficiently small to substantially fill the recessed microstructures; and

subjecting the electrolytically deposited copper layer to an annealing process at a temperature above an ambient temperature and at or below about 250 to 300 degrees Celsius to increase the copper grain size.

15. A method as claimed in claim 14 wherein the step of preparing a surface of the workpiece comprises:

applying at least one adhesion layer over the dielectric layer; and

applying a seed layer over the adhesion layer.

16. A method as claimed in claim 14 wherein the step of preparing a surface of the workpiece comprises:

applying at least one barrier layer over the dielectric layer; and

applying a seed layer over the barrier layer.

17. A method as claimed in claim 16 wherein the step of applying the seed layer is defined by applying the seed layer using a chemical vapor deposition process.

18. A method as claimed in claim 16 wherein the step of applying the seed layer is defined by applying the seed layer using a physical vapor deposition process.

19. A method as claimed in claim 14 wherein the step of removing the copper metallization is defined by removing the copper metallization using a chemical mechanical polish technique.

20. A method for filling recessed microstructures at a surface of a semiconductor workpiece with copper metal comprising:

providing a semiconductor workpiece with a feature that is to be connected with copper metallization;

applying at least one low-K dielectric layer over a surface of the semiconductor workpiece including the feature;

providing recessed microstructures in the at least one low-K dielectric layer;

preparing a surface of the workpiece, including the recessed microstructures, with a barrier layer and a continuous non-alloyed copper seed layer on the barrier layer for subsequent electrolytic copper deposition;

electrolytically depositing copper onto the seed layer to form continuous copper in the recessed microstructures using an electrolytic plating process that. generates copper grains having a size sufficiently small to substantially fill the recessed microstructures; and

subjecting the electrolytically deposited copper layer to an annealing process at a temperature above an ambient temperature and below which the low-K dielectric layer substantially degrades.

21. A method as claimed in claim 20 wherein the annealing step takes place at a temperature corresponding to a baking temperature of the low-K dielectric.

22. The method of claim 20 wherein the temperature of the elevated temperature annealing process is between about 60 degrees Celsius and about 100 degrees Celsius.

23. The method of claim 20 wherein the surface of the semiconductor workpiece is subjected to the elevated temperature annealing process for no longer than 15 minutes.

24. The method of claim 20 wherein the surface of the semiconductor workpiece is subjected to the elevated temperature annealing process for less than one minute.

25. The method of claim 20 wherein the predetermined temperature is at or below about 300 degrees Celsius.

26. The method of claim 20 wherein the predetermined temperature is at or below about 250 degrees Celsius.

27. The method of claim 20 wherein the predetermined temperature is at or below about 100 degrees Celsius.

28. The method of claim 20 wherein the electroplating power is initially applied at a first current for a predetermined first period of time, then applied at a higher second current for a predetermined second period of time.

29. The method of claim 20 wherein the surface of the workpiece is contacted with the electroplating solution for a predetermined dwell period before the electroplating power is applied.

30. The method of claim 20 wherein the electroplating power is applied as a direct current.

31.The method of claim 20 wherein the electroplating power is applied as a forward pulsed waveform at a frequency of between 1 and 1000 Hz.

33. The method of claim 20 wherein the copper is deposited via electroplating for a period of time sufficient to deposit excess copper which extends above the surface of the workpiece.

31. The method of claim 31 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.

32. The method of claim 31 wherein the workpiece is spun while electroplating power is applied.

34. The method of claim 34 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing.

35. The method of claim 35 wherein the excess copper is removed via chemical mechanical polishing.

36. A method of processing a semiconductor workpiece having a surface including a sub-micron recessed microstructure, comprising:

forming a continuous non-alloyed copper seed layer over a barrier layer in the recessed microstructure;

thereafter, electroplating copper to form continuous copper within the recessed microstructure and to deposit excess copper which extends above the surface of the workpiece;

thereafter, thermally treating the electroplated copper at a temperature of about 60 degrees Celsius to about 100 degrees Celsius for no longer than 15 minutes, thereby reducing resistivity of the copper; and

thereafter, removing the excess copper.

37. The method of claim 37 wherein the excess copper is removed via chemical mechanical polishing.

38. The method of claim 37 wherein an electroplating waveform is used, at least in part, to ensure sufficiently small grain size in the electroplated copper to substantially fill the recessed microstructure.

39. The method of claim 37 wherein an electroplating solution additive is used, at least in part, to ensure sufficiently small grain size in the electroplated copper to substantially fill the recessed microstructure.

40. The method of claim 37 wherein the recessed microstructure is defined, at least in part, as a recess in a dielectric layer, the method further comprising applying a barrier over the dielectric layer before depositing the seed layer.

41. The method of claim 41 wherein the seed layer is deposited on the barrier layer using a physical vapor deposition process.

42. A method of treating a semiconductor workpiece having a base having a surface, a dielectric layer carried on the surface of the base, and recessed sub-micron structures formed in the dielectric layer, comprising:

forming a continuous non-alloyed copper seed layer on a barrier layer over the dielectric layer and in the recessed sub-micron structures;

contacting the seed layer with a copper-containing electroplating solution;

after a predetermined dwell time, applying electroplating power to the seed layer to electrolytically deposit copper metal from the electroplating solution onto the seed layer to fill the recessed sub-micron structures with continuous copper and to deposit excess copper metal which extends above a surface of the dielectric layer;

then

reducing resistivity of the electrolytically deposited copper metal by subjecting the workpiece to an elevated temperature annealing process at a temperature that is above an ambient temperature and at or below about 250 degrees Celsius.

43. The method of claim 43 wherein the annealing process is carried out at a temperature that is at or below about 100 degrees Celsius.

44. The method of claim 43 wherein the annealing process is carried out at a temperature that is between about 60 degrees Celsius and about 100 degrees Celsius.

45. The method of claim 43 wherein the workpiece is subjected to the annealing process for no longer than 15 minutes.

46. The method of claim 43 wherein the workpiece is subjected to the annealing process for less than one minute.

47. The method of claim 43 wherein the resistivity is reduced by greater than 10% in the elevated temperature annealing process.

48. The method of claim 43 further comprising depositing a barrier layer on the dielectric layer and in the sub-micron structures prior to depositing the seed layer.

49. The method of claim 43 wherein the electroplating power is initially applied at a first current for a predetermined first period of time, then applied at a higher second current for a predetermined second period of time.

50. The method of claim 43 wherein the electroplating power is applied as a direct current.

51. The method of claim 43 wherein the electroplating power is applied as a forward pulsed waveform at a frequency of between 1 and 1000 Hz.

53. The method of claim 43 wherein the workpiece is spun while electroplating power is applied.

54. The method of claim 43 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing process.

52. The method of claim 52 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.

55. A method of treating a semiconductor workpiece having a base having a surface, a dielectric layer carried on the surface of the base, recessed sub-micron structures formed in the dielectric layer, and a barrier layer on the dielectric layer, comprising:

forming a continuous non-alloyed copper seed layer on the barrier layer and in the recessed sub-micron structures;

contacting the seed layer with a copper-containing electroplating solution;

applying electroplating power to the seed layer a first power level for a predetermined first period of time, then applying electroplating power to the seed layer a higher second power level for a time sufficient to electrolytically fill the recessed sub-micron structures with continuous copper metal and to deposit excess copper metal which extends above a surface of the dielectric layer;

then

reducing resistivity of the electrolytically deposited copper metal by subjecting the workpiece to an elevated temperature annealing process at a temperature that is above an ambient temperature and at or below about 250 degrees Celsius.

56. The method of claim 56 wherein the annealing process is carried out at a temperature that is at or below about 100 degrees Celsius.

57. The method of claim 56 wherein the annealing process is carried out at a temperature that is between about 60 degrees Celsius and about 100 degrees Celsius.

58. The method of claim 56 wherein the workpiece is subjected to the annealing process for no longer than 15 minutes.

59. The method of claim 56 wherein the workpiece is subjected to the annealing process for less than one minute.

60. The method of claim 56 wherein the resistivity is reduced by greater than 10% in the elevated temperature annealing process.

61. The method of claim 56 further comprising depositing a barrier layer on the dielectric layer and in the sub-micron structures prior to depositing the seed layer.

62. The method of claim 56 wherein the seed layer is contacted with the electroplating solution for a predetermined dwell period before the electroplating power is applied.

63. The method of claim 56 wherein the electroplating power is applied as a direct current.

64. The method of claim 56 wherein the electroplating power is applied at the second power level as a forward pulsed waveform at a frequency of between 1 and 1000 Hz.

66. The method of claim 56 wherein the workpiece is spun while electroplating power is applied.

67. The method of claim 56 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing process.

65. The method of claim 65 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.

68. A method of treating a semiconductor workpiece having a base having a surface, a dielectric layer carried on the surface of the base, recessed sub-micron structures formed in the dielectric layer, and a barrier layer on the dielectric layer, comprising:

forming a continuous non-alloyed copper seed layer on the barrier layer and in the recessed sub-micron structures;

contacting the seed layer with a copper-containing electroplating solution;

applying electroplating power to the seed layer in a forward pulsed waveform at a frequency of between 1 and 1000 Hz to electrolytically fill the recessed sub-micron structures with continuous copper metal and to deposit excess copper metal which extends above a surface of the dielectric layer;

then

reducing resistivity of the electrolytically deposited copper metal by subjecting the workpiece to an elevated temperature annealing process at a temperature that is above an ambient temperature and at or below about 250 degrees Celsius.

69. The method of claim 69 wherein the frequency is between 5 and 20 Hz with a duty cycle of at least 50 percent.

70. The method of claim 69 wherein the forward pulsed waveform has a duty cycle of 50-95 percent.

71. The method of claim 69 wherein the annealing process is carried out at a temperature that is at or below about 100 degrees Celsius.

72. The method of claim 69 wherein the annealing process is carried out at a temperature that is between about 60 degrees Celsius and about 100 degrees Celsius.

73. The method of claim 69 wherein the workpiece is subjected to the annealing process for no longer than 15 minutes.

74. The method of claim 69 wherein the workpiece is subjected to the annealing process for less than one minute.

75. The method of claim 69 wherein the resistivity is reduced by greater than 10% in the elevated temperature annealing process.

76. The method of claim 69 further comprising depositing a barrier layer on the dielectric layer and in the sub-micron structures prior to depositing the seed layer.

77. The method of claim 69 wherein the seed layer is contacted with the electroplating solution for a predetermined dwell period before the electroplating power is applied.

78. The method of claim 69 wherein the electroplating power is initially applied at a first current for a predetermined first period of time, then applied at a higher second current for a predetermined second period of time, the second current comprising the forward pulsed waveform.

79. The method of claim 69 wherein the workpiece is spun while electroplating power is applied.

80. The method of claim 69 further comprising removing the excess copper after the workpiece is subjected to the elevated temperature annealing process.