Semiconductor substrate having a stepped profile

• US 7,245,002 B2
• Filed: 05/13/2002
• Issued: 07/17/2007
• Est. Priority Date: 02/04/1998
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Atoji, Tadashi, Akino, Yutaka
• Primary Examiner(s): Nadav; Ori
• Application Number:
  US10/143,015
• Publication Number:
  US 20020132451A1
• Time in Patent Office: 1,891 Days
• Field of Search: 257/347, 257/618, 257/623, 257/626
• US Class Current: 257/623
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: Y10T 156/10 Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 156/1043 Subsequent to assembly
• CPC Class Codes: Y10T 156/1052 with cutting, punching, tearing or severing

Abstract

A semiconductor substrate which effectively prevents a chipping phenomenon, wherein the outer peripheral extremity of the insulation layer is located between the outer peripheral extremity of the semiconductor layer and the outer peripheral extremity of the support member, and wherein the semiconductor layer and the insulation layer produce a stepped profile.

Claims

1. A semiconductor substrate comprising a support member, an insulation layer arranged on the support member and a semiconductor layer arranged on the insulation layer,

wherein an outer peripheral extremity of said semiconductor layer is located inside an outer peripheral extremity of said support member, and an outer peripheral extremity of said insulation layer is located between the outer peripheral extremity of said semiconductor layer and the outer peripheral extremity of said support member, so that the outer peripheral portion of the semiconductor substrate, including said insulation layer and said semiconductor layer, shows a stepped profile,

wherein said insulation layer has a terrace on an upper surface of an outer peripheral portion thereof, wherein an offset between a bottom of the outer peripheral extremity of said semiconductor layer and a top of the outer peripheral extremity of said insulation layer is not smaller than 2 μ

m,

wherein an angle of inclination formed between a lateral surface of the outer peripheral portion of said insulation layer and a bottom surface of the insulation layer is not greater than 45°

,

wherein an lateral surface of an outer peripheral portion of said semiconductor layer also is inclined, and

wherein the angle of inclination between the lateral surface of the outer peripheral portion of said insulation layer and a bottom surface of said insulation layer is smaller than an angle of inclination between the lateral surface of said semiconductor layer and the bottom surface of said semiconductor layer.