Predictive, adaptive power supply for an integrated circuit under test

• US 7,245,120 B2
• Filed: 09/27/2005
• Issued: 07/17/2007
• Est. Priority Date: 01/18/2000
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Eldridge, Benjamin N.
• Primary Examiner(s): Nguyen; Ha Tran
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/237,092
• Publication Number:
  US 20060022699A1
• Time in Patent Office: 658 Days
• Field of Search: None
• US Class Current: 324/754.07
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT'"'"'s demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT'"'"'s power input terminal.

Claims

1. A method of testing a semiconductor device using a test apparatus, comprising:

creating a demand record of expected input demand at a power terminal of the semiconductor device correlated in time with a test sequence for the semiconductor device;

testing the semiconductor device in accordance with the test sequence; and

providing during the testing power to the semiconductor device in accordance with the demand record, wherein the providing power comprises;

generating a first supply of power to the power terminal of the semiconductor device; and

selectively generating a second supply of power to the power terminal of the semiconductor device in accordance with the demand record such that the second supply of power is provided substantially concurrently with an expected increase in demand for current at the power terminal.

2. The method of claim 1, wherein the providing power comprises using the demand record to adjust the behavior of the test apparatus.

3. The method of claim 1, wherein the providing power further comprises generating a timing signal to regulate an amount of the second supply of power provided to the power terminal of the semiconductor device.

4. The method of claim 1, wherein creating the demand record comprises applying signals to a reference semiconductor device and measuring a power demand of the reference semiconductor device with respect to time.

5. The method of claim 1, wherein creating the demand record comprises simulating a power demand of the semiconductor device with respect to time.

6. The method of claim 1, wherein the generating a second supply of power comprises providing the second supply of power to the semiconductor device correlated in time to test cycles of the test sequence.

7. The method of claim 1, wherein the input is voltage.

8. The method of claim 1, wherein the input is power.

9. The method of claim 1, wherein the input is current.

10. The method of claim 1, wherein the testing includes using a probe card.

11. A testing apparatus for a semiconductor device, comprising:

a demand recorder for recording a demand record of expected input demand at a power terminal of the semiconductor device correlated in time with a test sequence for the semiconductor device; and

a probe card configured to facilitate testing the semiconductor device in accordance with the test sequence; and

power means for providing power to the semiconductor device in accordance with the demand record, wherein the power means comprises;

a primary power supply for providing a supply of power to the power terminal of the semiconductor device; and

an auxiliary power supply for providing an auxiliary supply of power to the power terminal in accordance with the demand record such that the auxiliary supply of power is provided substantially concurrently with an increase in demand for current at the power terminal.

12. The testing apparatus of claim 11, wherein the auxiliary power supply is disposed on the probe card.