Memory module and method having improved signal routing topology

• US 7,245,145 B2
• Filed: 06/11/2003
• Issued: 07/17/2007
• Est. Priority Date: 06/11/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Greeff, Roy E., Pax, George E.
• Primary Examiner(s): Le; Don
• Assistant Examiner(s): Mai; Lam T.
• Application Number:
  US10/460,588
• Publication Number:
  US 20040251929A1
• Time in Patent Office: 1,497 Days
• Field of Search: 326/30, 326 80- 85, 326/86, 327/565, 438/253, 345/501, 365190-195, 245/501
• US Class Current: 326/30
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H05K 1/025 Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H01L23/66
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09254 Branched layout
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Claims

1. A memory module, comprising:

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals, the active memory component further having a register for storing address and command signals and outputting the stored address and command signals to the memory devices; and

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end.

2. The memory module of claim 1 wherein each of the transmission lines in each branch has a characteristic impedance, and wherein the characteristic impedance of each transmission line is approximately half the characteristic impedance of any transmission line to which it is coupled downsteam of the active memory component.

3. The memory module of claim 1 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

4. The memory module of claim 1, further comprising:

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

5. The memory module of claim 4 wherein the additional memory device comprises an error checking memory device.

6. The memory module of claim 4 wherein the length of the dedicated transmission line provides substantially the same propagation time as the transmission lines from the active memory component to the plurality of memory devices.

7. The memory module of claim 1 wherein the memory module comprises 2^N of the memory devices, and wherein the symmetrical tree comprise N hierarchies of branches.

8. The memory module of claim 7 wherein the memory module comprises 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy as the hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

9. A memory module, comprising:

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals, the active memory component further having a register for storing address and command signals and outputting the stored address and command signals to the memory devices; and

a plurality of transmission lines coupling a plurality of the output terminals of the active memory device to respective input terminals of the memory devices, each of the transmission lines being connected at only its ends to either one of the input terminals of one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same length.

10. The memory module of claim 9 wherein each of the transmission lines has a characteristic impedance, and wherein the characteristic impedance of each transmission line is approximately half the characteristic impedance of any transmission line to which it is coupled downsteam of the active memory component.

11. The memory module of claim 9 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

12. The memory module of claim 9, further comprising:

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

13. The memory module of claim 12 wherein the additional memory device comprises an error checking memory device.

14. The memory module of claim 12 wherein the length of the dedicated transmission line provides substantially the same propagation time as the length of the transmission lines from the active memory component to the plurality of memory devices.

15. The memory module of claim 9 wherein the memory module comprises 2^N of the memory devices, and wherein the transmission lines are arranged in N hierarchies of levels.

16. The memory module of claim 15 wherein the memory module comprises 4 memory devices, and wherein the transmission lines are arranged in a first branch having a first level of hierarchy, a second branch having a second level of hierarchy that is lower than the hierarchy of the first branch, and a third branch having the same hierarchy as the hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

17. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals, the active memory component further having a register for storing address and command signals and outputting the stored address and command signals to the memory devices; and

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end.

18. The processor-based system of claim 17 wherein each of the transmission lines in each branch has a characteristic impedance, and wherein the characteristic impedance of each transmission line is approximately half the characteristic impedance of any transmission line to which it is coupled downsteam of the active memory component.

19. The processor-based system of claim 18 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

20. The processor-based system of claim 17, further comprising:

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

21. The processor-based system of claim 20 wherein the additional memory device comprises an error checking memory device.

22. The processor-based system of claim 20 wherein the length of the dedicated transmission line provides substantially the same propagation time as the transmission lines from the active memory component to the plurality of memory devices.

23. The processor-based system of claim 17 wherein the memory module comprises 2^N of the memory devices, and wherein the symmetrical tree comprise N hierarchies of branches.

24. The processor-based system of claim 23 wherein the memory module comprises 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy as the hierarchy of the second branch, the transmission lines in the third and fourth branches being coupled to respective ones of the memory devices.

25. A method of coupling signals from an active memory component in a memory module to a plurality of memory devices in the memory module, the method comprising:

storing a plurality of signals including address and command signals in the active memory component, and outputting the stored plurality of signals; and

coupling the plurality of signals from the active memory component to the memory devices through a plurality of transmission lines in which each transmission line is connected at only its ends to either one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same length.

26. The method of claim 25 wherein each of the transmission lines has a characteristic impedance, and wherein the act of coupling a plurality of the signals from the active memory component to the memory devices through a plurality of transmission lines comprises coupling each of the signals from upstream transmission lines to downstream transmission lines in which the characteristic impedance of each downstream transmission line is twice the characteristic impedance of the upstream transmission line to which it is coupled.

27. The method of claim 25 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

28. The method of claim 25, further comprising coupling signals from the active memory component to an additional memory device mounted on the memory module substrate other than the plurality of memory devices, the method comprising coupling a plurality of the signals from the active memory component to the additional memory device through a dedicated transmission line that is not directly connected to any of the plurality of memory devices.

29. The method of claim 28 wherein the length of the dedicated transmission line provides substantially the same propagation time as the length of the transmission lines from the active memory component to the plurality of memory devices.

30. The method of claim 25 wherein the plurality of memory devices comprise 2^N of the memory devices, and wherein the act of coupling a plurality of the signals from the active memory component to the memory devices through a plurality of transmission lines comprises arranging the transmission lines in N levels of hierarchy.

31. A memory module, comprising:

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals;

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end, and each transmission line in each branch having a characteristic impedance that is approximately half the characteristic impedance of any transmission line to which it is coupled downstream of the active memory component.

32. The memory module of claim 31 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

33. The memory module of claim 31, further comprising:

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

34. The memory module of claim 33 wherein the additional memory device comprises an error checking memory device.

35. The memory module of claim 33 wherein the length of the dedicated transmission line provides substantially the same propagation time as the transmission lines from the active memory component to the plurality of memory devices.

36. The memory module of claim 31 wherein the memory module comprises 2^N of the memory devices, and wherein the symmetrical tree comprise N hierarchies of branches.

37. The memory module of claim 36 wherein the memory module comprises 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

38. A memory of module, complaining:

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals;

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end;

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

39. The memory module of claim 38 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

40. The memory module of claim 38 wherein the additional memory device comprises an error checking memory device.

41. The memory module of claim 38 wherein the length of the dedicated transmission line provides substantially the same propagation time as the transmission lines from the active memory component to the plurality of memory devices.

42. The memory module of claim 38 wherein the memory module comprises 2^N of the memory devices, and wherein the symmetrical tree comprise N hierarchies of branches.

43. The memory module of claim 42 wherein the memory module comprises 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy as the hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

44. A memory module comprising:

a plurality of memory devices having 2^N number of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals; and

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree having N hierarchies of branches, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end.

45. The memory module of claim 44 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

46. The memory module of claim 44 wherein the memory module comprises a 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy as the hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

47. A memory module, comprising:

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals; and

a plurality of transmission lines coupling a plurality of the output terminals of the active memory devices to respective input terminals of the memory devices, each of the transmission lines being coupled at only its ends to either one of the input terminals of one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same length, each of the transmission lines further having a characteristic impedance that is approximately half the characteristic impedance of any transmission line to which it is coupled downstream of the active memory component.

49. The memory module of claim 47, further comprising:

an additional memory device other than the plurality of memory devices; and

a dedicated line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

50. The memory module of claim 49 wherein the additional memory device comprises an error checking memory device.

51. The memory module of claim 49 wherein the length of the dedicated transmission line provides substantially the same propagation time as the length of the transmission lines from the active memory component to the plurality of memory devices.

52. The memory module of claim 47 wherein the memory module comprises 2^N of the memory devices, and wherein the transmission lines are arranged in N hierarchies of levels.

53. The memory module of claim 52 wherein the memory module comprises 4 memory devices, and wherein the transmission lines are arranged in a first branch having a first level of hierarchy, a second branch having a second level of hierarchy that is lower than the hierarchy of the first branch, and a third branch having the same hierarchy as the hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

48. The memory module devices wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

54. A memory module, comprising:

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals;

a plurality of transmission lines coupling a plurality of the output terminals of the active memory device to respective input terminals of the memory devices, each of the transmission lines being connected at only its ends to either one of the input terminals of one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same length;

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of the several of the output terminals of the active memory component to respective input terminals of the additional memory device.

55. The memory module of claim 54 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

56. The memory module of claim 54 wherein the additional memory device comprises an error checking memory device.

57. The memory module of claim 54 wherein the length of the dedicated transmission line provides substantially the same propagation time as the length of the transmission lines from the active memory component to the plurality of memory devices.

58. The memory module of claim 54 wherein the memory module comprises 2^N of the memory devices, and wherein the transmission lines are arranged in N hierarchies of levels.

59. The memory module of claim 58 wherein the memory module comprises 4 memory devices, and wherein the transmission lines are arranged in a first branch having a first level of hierarchy, a second branch having a second level of hierarchy that is lower than the hierarchy of the first branch, and a third branch having the same hierarchy as the hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

60. A memory module, comprising:

a plurality of memory devices having 2^N number of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals; and

a plurality of transmission lines coupling a plurality of the output terminals of the active memory device to respective input terminals of the memory devices, each of the transmission lines being connected at only its ends to either one of the input terminals of one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in N hierarchies of levels with the transmission lines in the same hierarchy having the same length.

61. The memory module of claim 60 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

62. The memory module of claim 61 wherein the memory module comprises 4 memory devices, and wherein the transmission lines are arranged in a first branch having a first level of hierarchy, a second branch having a second level of hierarchy that is lower than the hierarchy of the first branch, and a third branch having the same hierarchy as the hierarchy of the second branch, the transmission lines in the second and third branches being coupled to respective ones of the memory devices.

63. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals; and

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end, and each transmission line in each branch having a characteristic impedance that is approximately half the characteristic impedance of any transmission line to which it is coupled downstream of the active memory component.

64. The processor-based system of claim 63 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

65. The processor-based system of claim 63, further comprising:

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

66. The processor-based system of claim 65 wherein the additional memory device comprises an error checking memory device.

67. The processor-based system of claim 65 wherein the length of the dedicated transmission line provides substantially the same propagation time as the transmission lines from the active memory component to the plurality of memory devices.

68. The processor-based system of claim 63 wherein the memory module comprises 2^N of the memory devices, and wherein the symmetrical tree comprise N hierarchies of branches.

69. The processor-based system of claim 68 wherein the memory module comprises 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy as the hierarchy of the second branch, the transmission lines in the third and fourth branches being coupled to respective ones of the memory devices.

70. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals;

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end;

an additional memory device other than the plurality of memory devices; and

a dedicated transmission line coupling each of several of the output terminals of the active memory component to respective input terminals of the additional memory device.

71. The processor-based system of claim 70 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

72. The processor-based system of claim 70 wherein the additional memory device comprises an error checking memory device.

73. The processor-based system of claim 70 wherein the length of the dedicated transmission line provides substantially the same propagation time as the transmission lines from the active memory component to the plurality of memory devices.

74. The processor-based system of claim 70 wherein the memory module comprises 2^N of the memory devices, and wherein the symmetrical tree comprise N hierarchies of branches.

75. The processor-based system of claim 74 wherein the memory module comprises 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy as the hierarchy of the second branch, the transmission lines in the third and fourth branches being coupled to respective ones of the memory devices.

76. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices having 2^N number of memory devices;

an active memory component having a plurality of input terminals and a plurality of output terminals; and

a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree having N hierarchies of branches, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end.

77. The processor-based system of claim 76 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

78. The processor-based system of claim 76 wherein the memory module comprises 4 memory devices, and wherein the symmetrical tree comprises a first branch having a pair of transmission lines, a second branch having a pair of transmission lines and having a hierarchy lower than the hierarchy of the first branch, and a third branch having a pair of transmission lines and having the same hierarchy as the hierarchy of the second branch, the transmission lines in the third and fourth branches coupled to respective ones of the memory devices.

79. A method of coupling signals from an active memory component in a memory module to a plurality of memory devices in the memory module, the method comprising:

coupling a plurality of the signals from the active memory component to the memory devices through a plurality of transmission lines in which each transmission line is connected at only its end to either one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same lenght; and

coupling each of the plurality of signals from upstream transmission lines to downstream transmission lines in which a characteristics impedance of each downstream transmission line is twice the characteristic impedance of the upstream tranmission line to which is coupled.

80. The method of claim 79 wherein the plurality of memory devices comprises a plurality of dynamic random a access memory devis.

81. The method of claim 79, further comprising coupling signals from the active memory component to an additional memory device mounted on the memory module substrate other than the plurality of memory devices, the method comprising coupling a plurality of the signals from the active memory component to the additional memory device through a dedicated transmission line that is not directly connected to any of the plurality of memory devices.

82. The method of claim 81 wherein the length of the dedicated transmission line provides substantially the same propagation time as the length of the transmission lines from the active memory component to the plurality of memory devices.

83. The method of claim 79 wherein the plurality of memory devices comprise 2^N of the memory devices, and wherein the act of coupling a plurality of the signals from the active memory component to the memory devices through a plurality of transmission lines comprises arranging the transmission lines in N levels of hierarchy.

84. A method of coupling signals from an active memory component in a memory module to a plurality of memory devices in the memory module, the method comprising:

coupling a plurality of the signals from the active memory component to the memory devices through a plurality of transmission lines in which each transmission line is connected at only its ends to either one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same length; and

coupling signals from the active memory component to an additional memory device mounted on the memory module substrate other than the plurality of memory devices, the plurality of the signals from the active memory component to the additional memory device being coupled through a dedicated transmission line that is not directly connected to any of the plurality of memory devices.

85. The method of claim 84 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

86. The method of claim 84 wherein the length of the dedicated transmission line provides substantially the same propagation time as the length of the transmission lines from the active memory component to the plurality of memory devices.

87. The method of claim 84 wherein the plurality of memory devices comprise 2^N of the memory devices, and wherein the act of coupling a plurality of the signals from the active memory component to the memory devices through a plurality of transmission lines comprises arranging the transmission lines in N levels of hierarchy.

88. A method of coupling signals from an active memory component in a memory module to a plurality of memory devices in the memory module, the method comprising:

coupling 2^N of the memory devices to the active memory component; and

coupling the plurality of the signals from the active memory component to the 2^N of the memory devices through a plurality of transmission lines in which each transmission line is connected at only its ends to either one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in N levels of hierarchy with the transmission lines in the same hierarchy having the same length.

89. The method of claim 88 wherein the plurality of memory devices comprise a plurality of dynamic random access memory devices.