Clock modulation systems

• US 7,245,668 B2
• Filed: 12/10/2005
• Issued: 07/17/2007
• Est. Priority Date: 08/31/1998
• Status: Expired due to Fees

• Current Assignee: Kamilo Feher
• Original Assignee: Kamilo Feher
• Inventors: Feher, Kamilo
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US11/299,344
• Publication Number:
  US 20060088121A1
• Time in Patent Office: 584 Days
• Field of Search: 375/257, 375/259, 375/295, 375/354, 713/501
• US Class Current: 375/295
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/0004 using wavelets
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/2637 with direct modulation of individual subcarriers
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

Shaped Clocked (SC) and Clock Modulation (CM) systems, signal generation-reception, processing and CM implementations. Systems having a first and second shaped clock signal and providing shaped clocks to a selector switch and to a signal transmitter. The selectable clock signal parameters include symmetrical and non-symmetrical shaped clock signals, shaped filtered continuous clock signal patterns, shaped encoded clock signals, variable rise and fall time clock signals, clock signals having shaped adjustable on and off duration, multilevel and shaped clock signals and asynchronous clock signal information transmission means. The Clock Modulation (CM), Shaped Clocked (SC) systems, also designated as Feher Keying (FK) systems or FK processors are also used in conjunction with cross-correlated quadrature and also non quadrature modem systems as input drive signals to FM VCO based systems, to SSB to VSB to DSB-SC to QAM, and/or to coded systems.

Claims

1. A dock modulation system comprising:

a clock modulator generating Bit Rate Agile (BRA) clock shaped, clock modulated signals;

a modulator filter band limiting the said modulated signals;

a signal transmitter transmitting the clock modulated bandlimited signals;

a receiver and demodulator for reception and demodulation of clock modulated signals; and

a Bit Rate Agile (BRA) demodulator filter for filtering the received signals said demodulator filter having intentionally miss-matched filter parameters to that of the modulator filter.

2. The method as in claim 1 wherein the clock modulated signals are two separate signals, with one having different amplitude than the other signal.

3. The method as in claim 1 wherein the clock modulated signals have changeable distance between the rising edges and falling edges.

4. The method as in claim 1 wherein one clock modulated signal has a shorter time duration than the other clock modulated signal.

5. The method as in claim 1 wherein the signal transmitter comprises of a linear amplifier, a non-linear amplifier and a selector switch for selection of the linearly amplified or the non-linearly amplified signal.

6. The method as in claim 1 wherein the clock modulated signals comprise two distinct signal formats.

7. A system comprising:

an unit for providing a Bit Rate Agile (BRA) data signal to a clock modulator;

a clock modulator generating a first shaped and a second shaped BRA clock modulated signal and providing said first and second shaped BRA clock modulated signals to a selector switch;

a said selector switch for selecting the first or the second clock modulated signal and connecting the selected signal modulated to a signal transmitter filter;

a said transmitter filter band limiting the said modulated signals;

a signal transmitter transmitting the clock modulated bandlimited signals;

a receiver and demodulator for reception and demodulation of clock modulated signals; and

a Bit Rate Agile (BRA) demodulator filter for filtering the received signals.

8. The method as in claim 7 wherein the Bit Rate Agile (BRA) demodulator filter for filtering the received clock modulated signals is intentionally miss-matched filter to that of the transmitter filter.

9. The method as in claim 7 wherein the two shaped clock signals comprise two distinct signal formats, with one signal having shorter time duration than the other signal.

10. The method as in claim 7 wherein the two shaped lock signals comprise two distinct signal formats, with one signal having larger signal amplitude than the other signal.

11. A system comprising:

a data unit for providing a data signal to two clock generators;

a first clock generator generating a first shaped, non-symmetrical format clock signal and providing the first shaped clock signal to a selector switch;

a second clock generator generating a second shaped clock signal and providing the second shaped clock signal to the said selector switch;

said selector switch for selecting the first or the second shaped clock signal, having a first input interface port coupled to data controller signals, and a set of input ports coupled to the shaped clock signals and an output interface port coupled to said selector switch output.

12. The method as in claim 11 wherein the two shaped clock signals comprise two distinct signal formats, with one signal having larger signal amplitude than the other signal.

13. The method as in claim 11 wherein the said output interface port coupled to said selector switch output provides the selected shaped signal to a transmitter filter and a transmitter transmitting the clock modulated bandlimited signals and to a receiver and demodulator for reception and demodulation of clock modulated signal and to a Bit Rate Agile (BRA) demodulator filter for filtering the received signals.

14. The method as in claim 11 wherein the said output interface port coupled to said selector switch output provides the selected shaped signal to a modulator filter and a signal transmitter transmitting the signal to a receiver and demodulator for reception and demodulation of clock modulated signals and to a Bit Rate Agile (BRA) demodulator filter for filtering the received signals, wherein the demodulator filter for filtering the received clock modulated signals is intentionally miss-matched filter to that of the modulator filter.