System and method for compensating for skew between a first clock signal and a second clock signal

• US 7,245,684 B2
• Filed: 07/30/2003
• Issued: 07/17/2007
• Est. Priority Date: 05/09/2003
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Adkisson, Richard W.
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): BENGHUZZI, MOHSIN M
• Application Number:
  US10/630,317
• Publication Number:
  US 20040223570A1
• Time in Patent Office: 1,448 Days
• Field of Search: 375/371, 375/219, 375/226, 375/224, 375/354, 713/503
• US Class Current: 375/359
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A system and method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a phase detector is provided for detecting a phase between the first and second clock signals. A skew state detector disposed in communication with the phase detector is operable to generate a skew state signal which tracks a phase relationship between the clock signals. A synchronizer control signal generator responds to the skew state signal by generating at least one control signal to compensate for the skew between the first clock signal and the second clock signal.

Claims

1. A system for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧

1, the system comprising;

a phase detector operable to detect a phase difference between said first clock signal and said second clock signal;

a skew state detector disposed in communication with said phase detector for generating a skew state signal which tracks a phase relationship between said first clock signal and said second clock signal relative to a zero point of a timing window corresponding to said second clock signal; and

a synchronizer control signal generator, responsive to said skew state signal, for generating at least one control signal according to a value of said skew state signal.

2. The system as recited in claim 1, wherein said skew state signal is operable to compensate for greater than one clock period difference between said first clock signal and said second clock signal.

3. The system as recited in claim 1, wherein said at least one control signal is used to facilitate data transfer between said first clock domain and said second clock domain.

4. The system as recited in claim 1, wherein said zero point comprises an instance of coincident rising edges.

5. The system as recited in claim 1, wherein zero point comprises an instance of coincident falling edges.

6. The system as recited in claim 1, wherein said skew state detector generates said skew state signal (skew_state) in response to sampled clock signals (pd_b_cr and pd_b_cf) provided by said phase detector.

7. The system as recited in claim 1, wherein said at least one control signal comprises an indication whether a current data transfer contains valid data.

8. The system as recited in claim 1, wherein said at least one control signal is selected from the signal group comprising c0_sel, cl_sel, core_sel, b2c_valid, c2b_valid, and c2b_valid_m.

9. A method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧

1, the method comprising;

determining a phase difference between said first clock signal and said second clock signal relative to a zero point of a timing window corresponding to said second clock signal;

deciding if a state transition is necessary based on a result of said determining step; and

generating a control signal indicative of said state transition, thereby compensating for said skew between said first clock signal and said second clock signal.

10. The method as recited in claim 9, wherein the operation of determining a phase difference between said first clock signal and said second clock signal determines the phase difference to be at least one quarter cycle apart.

11. The method as recited in claim 9, wherein said state transition comprises a transition that tracks a negative skew difference between said first and second clock signals.

12. The method as recited in claim 9, wherein said state transition comprises a transition that tracks a positive skew difference between said first and second clock signals.

13. The method as recited in claim 9, wherein said control signal is operable to indicate that no skew state transition is necessary.

14. The method as recited in claim 9, wherein said control signal is indicative of a temporal relationship between said coincident edges and said second clock signal.

15. A computer system having an apparatus for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/N≧

1, the computer system comprising;

means for determining a phase difference between said first clock signal and said second clock signal relative to a zero point of a timing window corresponding to said second clock signal;

means for deciding if a state transition is necessary based on a result of said determining; and

means for generating a control signal indicative of said state transition, thereby compensating for said skew between said first clock signal and said second clock signal.

16. The computer system as recited in claim 15, wherein said means for determining a phase difference between said first clock signal and said second clock signal comprises means for determining said first clock signal and said second clock signal to be at least one quarter cycle apart.

17. The computer system as recited in claim 15, wherein said state transition comprises a transition that tracks a negative skew difference between said first and second clock signals.

18. The computer system as recited in claim 15, wherein said state transition comprises a transition that tracks a positive skew difference between said first and second clock signals.

19. The computer system as recited in claim 15, wherein said control signal is operable to indicate that no skew state transition is necessary.

20. The computer system as recited in claim 15, wherein said control signal is indicative of a temporal relationship between said coincident edges and said second clock signal.