Shift register and electronic device using the same

• US 7,245,690 B2
• Filed: 05/19/2005
• Issued: 07/17/2007
• Est. Priority Date: 05/20/2004
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Mutaguchi, Kohei
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US11/132,446
• Publication Number:
  US 20050276369A1
• Time in Patent Office: 789 Days
• Field of Search: None
• US Class Current: 377/64
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 29/848 by adjacent switching
• CPC Class Codes: G11C 29/86 in serial access memories, e.g. shift registers, CCDs, bubble memories

Abstract

The invention provides a shift register which can function normally even with an abnormal register or a broken register while suppressing the manufacturing cost as little as possible. The shift register of the invention includes n regular registers (SR(1) to SR(n)) connected in series and n output lines (L1 to Ln) corresponding to the n regular registers, r (r≦n) redundant registers (SR(n+1) to SR(n+r)) connected in series to the n regular registers, and a switch circuit for selectively connecting the regular and redundant resistors to output lines. The switch circuit connects the n regular registers to the corresponding output lines in a normal state, connects normal registers of upper and lower stages of the broken register by skipping and disabling the broken register if any, and connects normal regular registers and the same number of redundant registers as the broken registers to the n output lines.

Claims

1. A shift register comprising:

n (n≧

1) regular registers connected in series;

n output lines;

r (n≧

r≧

1) redundant registers connected in series to the n regular registers; and

a circuit for selectively connecting the n regular registers and the r redundant registers to the n output lines,

wherein the circuit connects the n regular registers to the n output lines,

wherein the circuit connects a normal regular register of an upper stage than an abnormal regular register to a normal regular register of a lower stage than the abnormal regular register by skipping the abnormal regular register, includes a disable circuit which disables the abnormal regular register, and connects the normal regular registers and at least one redundant register to the n output lines, and

wherein the number of the redundant registers connected to the output line is the same number as that of the abnormal regular registers.

2. The shift register according to claim 1,

wherein the circuit comprises (n+r) switches,

wherein each of the (n+r) switches has a first terminal, a second terminal, a third terminal, and a control terminal,

wherein the first terminal is selectively connected to one of the second and third terminals in accordance with a control signal inputted to the control terminal,

wherein the first terminal is connected to one of the n regular registers and the r redundant registers, and

wherein the third terminal of a switch of an upper stage and the second terminal of a switch of a lower stage are connected between a pair of adjacent switches.

3. The shift register according to claim 1,

wherein the circuit comprises switches, and

wherein a switch of a bottom stage comprises a first terminal and a second terminal.

4. The shift register according to claim 1,

wherein the circuit comprises the disable circuit which disables the abnormal regular register which is determined to be broken from a state of the circuit.

5. The shift register according to claim 1,

wherein the circuit comprises buffer circuits,

wherein each of the buffer circuits is connected to one of the n regular registers and the r redundant registers, and

wherein the disable circuit stops an operation voltage supply to the buffer circuit connected to the abnormal regular register and makes a terminal of the abnormal regular register electrically floating.

6. The shift register according to claim 1,

wherein the circuit includes switches and a control signal line of which one end is connected to a low voltage source and the other end is connected to a high voltage source,

wherein a control terminal of each of the switches is connected to the control signal line,

wherein a voltage from one of the high voltage source and the low voltage source is supplied to the control terminal of each of the switches, and

wherein the control signal line is cut off between a selected switch and a switch of one stage lower than the selected switch so that a voltage from the other of the high voltage source and the low voltage source is supplied as the control signal to lower stage switches than the selected switch.

7. The shift register according to claim 1,

wherein the circuit includes switches and a control signal line,

wherein a control terminal of each of the switches is connected to the control signal line, and

wherein the control signal line comprises a fuse.

8. The shift register according to claim 1,

wherein the shift register is incorporated in a display device.

9. The shift register according to claim 8,

wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a mobile computer, an image reproducing device, a goggle type display, a video camera, a portable phone, and a navigation system.

10. A shift register comprising:

n (n≧

1) regular registers connected in series;

n output lines;

one redundant register connected in series to the n regular registers; and

a circuit for selectively connecting the n regular registers and the redundant register to the n output lines,

wherein the circuit comprises (n+1) switches,

wherein each of the (n+1) switches has a first terminal, a second terminal, a third terminal, and a control terminal,

wherein the first terminal is selectively connected to one of the second and third terminals in accordance with a control signal inputted to the control terminal,

wherein the first terminal is connected to one of the n regular registers and the redundant register,

wherein the third terminal of a switch of an upper stage and the second terminal of a switch of a lower stage are connected between a pair of adjacent switches,

wherein the circuit connects the n regular registers to the n output lines, and

wherein the circuit connects a normal regular register of an upper stage than an abnormal regular register to a normal regular register of a lower stage than the abnormal regular register by skipping the abnormal regular register, includes a disable circuit which disables the abnormal regular register, and connects the (n−

1) normal regular registers and the redundant register to the n output lines.

11. The shift register according to claim 10,

wherein the shift register is incorporated in a display device.

12. The shift register according to claim 11,

wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a mobile computer, an image reproducing device, a goggle type display, a video camera, a portable phone, and a navigation system.

13. A shift register comprising:

n (n≧

1) regular registers connected in series;

n output lines;

two redundant registers connected in series to the n regular registers; and

a circuit for selectively connecting the n regular registers and the two redundant registers to the n output lines,

wherein the circuit comprises (n+2) first switches and (n+1) second switches,

wherein each of the (n+2) first switches and the (n+1) second switches has a first terminal, a second terminal, a third terminal, and a control terminal,

wherein the first terminal is selectively connected to one of the second and third terminals in accordance with a control signal inputted to the control terminal,

wherein the first terminal of each of the (n+2) first switches is connected to one of the n regular registers and the two redundant registers,

wherein the third terminal of a first switch of an upper stage and the second terminal of a first switch of a lower stage are connected between a pair of adjacent first switches,

wherein the first terminal of each of the (n+1) second switches is connected to the third terminal of the first switch and the second terminal of the first switch of one stage lower,

wherein the third terminal of a second switch of an upper stage switch and the second terminal of a second switch of a lower stage are connected between a pair of adjacent second switches,

wherein the circuit connects the n regular registers to the n output lines,

wherein the circuit connects a normal regular register of an upper stage than an abnormal regular register to a normal regular register of a lower stage than the abnormal regular register by skipping the abnormal regular register, includes a disable circuit which disables the abnormal regular register, and connects the normal regular registers and at least one redundant register to the n output lines, and

wherein the number of the redundant registers connected to the output line is the same number as that of the abnormal regular registers.

14. The shift register according to claim 13,

wherein the shift register is incorporated in a display device.

15. The shift register according to claim 14,

wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a mobile computer, an image reproducing device, a goggle type display, a video camera, a portable phone, and a navigation system.

16. A shift register comprising:

n (n≧

1) regular registers connected in series;

n output lines;

two redundant registers connected in series to the n regular registers; and

a circuit for selectively connecting the n regular registers and the two redundant registers to the n output lines,

wherein the circuit comprises (n+2) first switches and (n+1) second switches,

wherein each of the (n+2) first switches and the (n+1) second switches has a first terminal, a second terminal, a third terminal, and a control terminal,

wherein the first terminal is selectively connected to one of the second and third terminals in accordance with a control signal inputted to the control terminal,

wherein the first terminal of each of the (n+2) first switches is connected to one of the n regular registers and the two redundant registers,

wherein the third terminal of a first switch of an upper stage and the second terminal of a first switch of a lower stage are connected between a pair of adjacent first switches,

wherein the first terminal of each of the (n+1) second switches is connected to the third terminal of the first switch and the second terminal of the first switch of one stage lower,

wherein the third terminal of a second switch of an upper stage switch and the second terminal of a second switch of a lower stage are connected between a pair of adjacent second switches,

wherein each of the n output lines is connected to the third terminal of one of the second switches and the second terminal of a second switch of one lower stage,

wherein the circuit includes first and second control signal lines each having one end connected to a low voltage source and the other end connected to a high voltage source,

wherein the control terminal of each of the (n+2) first switches is connected to the first control signal line,

wherein a voltage from one of the high voltage source and the low voltage source is supplied to the control terminal of the first switch,

wherein the control terminal of each of the second switches is connected to the second control signal line,

wherein a voltage from one of the high voltage source and the low voltage source is supplied to the control terminal of the second switch,

wherein the first control signal line is cut off between a selected first switch and a first switch of one stage lower so that a voltage from the other of the high voltage source and the low voltage source is supplied as the control signal to a first switch of lower stage than the selected first switch,

wherein the second control signal line is cut off between a selected second switch and a second switch of one stage lower so that a voltage from the other of the high voltage source and the low voltage source is supplied as the control signal to a second switch of lower stage than the selected second switch,

wherein the circuit connects the n regular registers to the n output lines,

wherein the circuit connects a normal regular register of an upper stage than an abnormal regular register to a normal regular register of a lower stage than the abnormal regular register by skipping the abnormal regular register, includes a disable circuit which disables the abnormal register, and connects the normal regular registers and at least one redundant register to the n output lines, and

wherein the number of the redundant registers connected to the output line is the same number as that of the abnormal regular registers.

17. The shift register according to claim 16,

wherein at least one of the first control signal line and the second control signal line comprises a fuse.

18. The shift register according to claim 16,

wherein the shift register is incorporated in a display device.

19. The shift register according to claim 18,

wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a mobile computer, an image reproducing device, a goggle type display, a video camera, a portable phone, and a navigation system.

20. A shift register comprising:

n (n≧

1) regular registers connected in series;

n output lines;

r (n≧

r≧

1) redundant registers connected in series to the n regular registers; and

a circuit for selectively connecting the n regular registers and the r redundant registers to the n output lines,

wherein the circuit connects i-th (n≧

i≧

1) regular register and (i+2)-th regular register by skipping (i+1)-th regular register when the (i+1)-th regular register is an abnormal regular register, and includes a disable circuit which disables the (i+1)-th regular register, and

wherein one of the r redundant registers is connected to one of the n output lines through the circuit.

21. The shift register according to claim 20,

wherein the circuit comprises (n+r) switches.

wherein each of the (n+r) switches has a first terminal, a second terminal, a third terminal, and a control terminal,

wherein the first terminal is selectively connected to one of the second and third terminals in accordance with a control signal inputted to the control terminal,

wherein the first terminal is connected to one of the n regular registers and the r redundant registers, and

wherein the third terminal of a switch of an upper stage and the second terminal of a switch of a lower stage switch are connected between a pair of adjacent switches.

22. The shift register according to claim 20,

wherein the circuit comprises switches, and

wherein a switch of a bottom stage comprises a first terminal and a second terminal.

23. The shift register according to claim 20,

wherein the circuit comprises the disable circuit which disables the abnormal regular register which is determined to be broken from a state of the circuit.

24. The shift register according to claim 20,

wherein the circuit comprises buffer circuits,

wherein each of the buffer circuits is connected to one of the n regular registers and the r redundant registers, and

wherein the disable circuit stops an operation voltage supply to the buffer circuit connected to the abnormal regular register and makes an output of the abnormal regular register electrically floating.

25. The shift register according to claim 20,

wherein the circuit includes switches and a control signal line of which one end is connected to a low voltage source and the other end is connected to a high voltage source,

wherein a control terminal of each of the switches is connected to the control signal line,

wherein a voltage from one of the high voltage source and the low voltage source is supplied to the control terminal of each of the switches, and

wherein the control signal line is cut off between a selected switch and a switch of one stage lower than the selected switch so that a voltage from the other of the high voltage source and the low voltage source is supplied as the control signal to lower stage switches than the selected switch.

26. The shift register according to claim 20,

wherein the circuit includes switches and a control signal line,

wherein a control terminal of each of the switches is connected to the control signal line, and

wherein the control signal line comprises a fuse.

27. The shift register according to claim 20,

wherein the shift register is incorporated in a display device.

28. The shift register according to claim 27,

wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a mobile computer, an image reproducing device, a goggle type display, a video camera, a portable phone, and a navigation system.